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9781402074165

Computer Architecture

by ;
  • ISBN13:

    9781402074165

  • ISBN10:

    1402074166

  • Format: Hardcover
  • Copyright: 2003-05-01
  • Publisher: Kluwer Academic Pub
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Summary

The one instruction set computer (OISC) is the ultimate reduced instruction set computer (RISC). In OISC, the instruction set consists of only one instruction, and then by composition, all other necessary instructions are synthesized. This is an approach completely opposite to that of a complex instruction set computer (CISC), which incorporates complex instructions as microprograms within the processor. Computer Architecture: A Minimalist Perspective examines computer architecture, computability theory, and the history of computers from the perspective of one instruction set computing - a novel approach in which the computer supports only one, simple instruction. This bold, new paradigm offers significant promise in biological, chemical, optical, and molecular scale computers. Features include: - Provides a comprehensive study of computer architecture using computability theory as a base. - Provides a fresh perspective on computer architecture not found in any other text. - Covers history, theory, and practice of computer architecture from a minimalist perspective. Includes a complete implementation of a one instruction computer. - Includes exercises and programming assignments. Computer Architecture: A Minimalist Perspective is designed to meet the needs of a professional audience composed of researchers, computer hardware engineers, software engineers computational theorists, and systems engineers. The book is also intended for use in upper division undergraduate students and early graduate students studying computer architecture or embedded systems. It is an excellent text for use as a supplement or alternative in traditional Computer Architecture Courses, or in courses entitled "Special Topics in Computer Architecture".

Table of Contents

Preface
Acknowledgements
One Instruction Set Computing
What is One Instruction Set Computing?
Why Study OISC?
A Look Ahead
Exercises
Instruction Sets
Elements of an Instruction
Operands
Instruction Formats
Core Set of Instructions
Addressing Modes
Exercises
Types of Computer Architecture
Overview
A Simple Taxonomy
Accumulator
Register-Memory
Register-Oriented
Exercises
Evolution of Instruction Sets
Motivation
Evolution of Microprocessors
Timeline
Exercises
CISC, RISC, OISC
CISC versus RISC
Is OISC a CISC or a RISC?
Processor Complexity
Exercises
OISC Architectures
Single Instruction Types
MOVE
Comparing OISC Models
Variants of SBN and MOVE
OISC Continuum
Exercises
Historical Review of OISC
Subtract and Branch if Negative (SBN)
MOVE-Based
Timeline
Exercises
Instruction Set Completeness
Instruction Set Completeness
A Practical Approach to Determining Completeness
Completeness of Two OISCs
Exercises
OISC Mappings
Mapping OISC to Conventional Architectures
Synthesizing Instructions
Code Fragments
Implementing OISC Using OISC
Exercises
Parallel Architectures
Von Neumann Bottleneck
Parallel Processing
Flynn's Taxonomy for Parallelism
Exercises
Applications and Implementations
OISC-Like Phenomena
Field Programmable Gate Arrays
Applications
Image Processing
Future Work with OISC
Exercises
A Generic Microprocessor and OISC
One Instruction Set Computer Implementation
Dilation Code Implementation
Compiler Output for Dilation
OISC Equivalent of Dilation
Glossary
References
Index
About the Authors
Table of Contents provided by Publisher. All Rights Reserved.

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