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| Preface | |
| Conference Organization | |
| "Real Time Distributed Systems (invited presentation)" | p. 1 |
| "Verification of the Futurebus+ Cache Coherence Protocol" | p. 15 |
| "Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation" | p. 31 |
| "Hardware-Verification using First Order BDDs" | p. 45 |
| "HW/SW Co-Design with PRAMs Using CoDES" | p. 65 |
| "Prevail-DM: A Framework-Based Environment for Formal Hardware Verification" | p. 79 |
| "Better Verification Through Symmetry" | p. 97 |
| "A Rewriting Based Method for the Formal Verification of Microprocessors" | p. 115 |
| "Reasoning about the VHDL Standard Logic Package Signal Data Type" | p. 123 |
| "An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area" | p. 131 |
| "Integrating Boolean Verification with Formal Derivation" | p. 139 |
| "Automated High-level Verification Against Clocked Algorithmic Specifications" | p. 147 |
| "The Backward Walk Approach in FSM Verification" | p. 155 |
| "Automatic Verification of Sequential Circuit Designs (invited presentation.)" | p. 163 |
| "Toward a Basis for Protocol Specification and Process Decomposition" | p. 169 |
| "Integrating SDL and VHDL for System-Level Hardware Design" | p. 187 |
| "Reasoning About Array Structures Using a Dependently Typed Logic" | p. 207 |
| "VHDL Description and Formal Verification of Systolic Multipliers" | p. 225 |
| "Transformational Rewriting with Ruby" | p. 243 |
| "A Representation for the Binding of RT-Component Functionality to HDL Behavior" | p. 263 |
| "Performance Specification and Measurement" | p. 281 |
| "Automatic Synthesis of Sequential Synchronizations" | p. 299 |
| "Specifying Hardware Systems in LOTOS" | p. 319 |
| "HML: A Hardware Description Language Based on Standard ML" | p. 327 |
| "An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems" | p. 335 |
| "Linking System Design Tools and Hardware Design Tools" | p. 345 |
| "Automatic VHDL Model Generation System" | p. 353 |
| "The Modeler's Assistant: A CAD Tool for Behavioral Model Development" | p. 361 |
| "Insulin: An Instruction Set Simulation Environment" | p. 369 |
| "Specification languages for communication protocols (invited presentation)" | p. 377 |
| "Integrating Behavior and Timing in Executable Specifications" | p. 399 |
| "ESP: An Executable Specification Language for Mixed Timing Control Circuits" | p. 417 |
| "UDL/I version Two: A New Horizon of HDL Standards" | p. 437 |
| "Verilog HDL Modeling Styles for Formal Verification" | p. 453 |
| "A Visual Hardware Description Language" | p. 467 |
| "Textual/Graphical Design Concept-Level Synthesis" | p. 485 |
| "System-Level Specification and Design Using VHDL: A Case Study" | p. 505 |
| "A Denotational Definition of the VHDL Simulation Kernel" | p. 523 |
| "Checking DFT Rules with a VHDL Simulator" | p. 537 |
| "Parameterized VHDL entities for the simulation of hybrid circuits" | p. 551 |
| "Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models" | p. 569 |
| "Analog-VHDL: As an application, a real example" | p. 587 |
| Table of Contents provided by Blackwell. All Rights Reserved. |
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The Used, Rental and eBook copies of this book are not guaranteed to include any supplemental materials. Typically, only the book itself is included. This is true even if the title states it includes any access cards, study guides, lab manuals, CDs, etc.
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