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Computer Organization and Architecture : Designing for Performance,9780130812940
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Computer Organization and Architecture : Designing for Performance

by
Edition:
5th
ISBN13:

9780130812940

ISBN10:
0130812943
Format:
Hardcover
Pub. Date:
7/1/1999
Publisher(s):
Prentice Hall
List Price: $105.00

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This is the 5th edition with a publication date of 7/1/1999.
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Summary

"Computer Organization & Architecture: Designing for Performance, Seventh Edition provides comprehensive, far-reaching, and up-to-date coverage of computer organization and architecture, including memory, I/O, and parallel systems. Author and consultant William Stallings systematically covers the state of the art, from superscalar and IA-64 design to the latest trends in parallel processor organization. Throughout, he illuminates fundamental principles, while focusing on the critical role of performance in driving computer design, and practical techniques for designing balanced systems that maximize utilization of all elements."--BOOK JACKET.

Author Biography

WILLIAM STALLINGS has made a unique contribution to understanding the broad sweep of technical developments in computer networking and computer architecture. He has authored 17 titles, plus revised editions, for a total of 37 books on various aspects of these subjects. He has three times received the award for best Computer Science Textbook of the Year from the Text and Academic Authors Association (Computer Organization and Architecture, Prentice Hall, 1996; Data and Computer Communications, Prentice Hall, 1997; Operating Systems, Prentice Hall, 1998). In over 20 years in the field, Dr. Stallings has been a technical contributor, technical manager and an executive with several high-technology firms. Currently he is an independent consultant whose clients have included computer and networking manufacturers and customers, software development firms and leading-edge government research institutions. Dr. Stallings is a frequent lecturer and a regular contributor to technical journals and trade publications. Dr. Stallings holds a Ph.D. from MIT in computer science and a B.S. from Notre Dame in electrical engineering.

Table of Contents

Web Site vi
Preface ix
PART I OVERVIEW 1(48)
Introduction
3(14)
Organization and Architecture
5(1)
Structure and Function
6(6)
Outline of the Book
12(3)
Internet and Web Resources
15(2)
Computer Evolution and Performance
17(32)
A Brief History of Computers
19(20)
Designing for Performance
39(4)
Pentium and PowerPC Evolution
43(3)
Recommended Reading and Web Sites
46(1)
Problems
47(2)
PART II THE COMPUTER SYSTEM 49(222)
System Buses
51(44)
Computer Components
53(3)
Computer Function
56(13)
Interconnection Structures
69(2)
Bus Interconnection
71(9)
PCI
80(9)
Recommended Reading and Web Sites
89(1)
Problems
90(5)
Appendix 3A: Timing Diagrams
92(3)
Internal Memory
95(58)
Computer Memory System Overview
97(6)
Semiconductor Main Memory
103(14)
Cache Memory
117(15)
Pentium II and PowerPC Cache Organizations
132(5)
Advanced DRAM Organization
137(5)
Recommended Reading and Web Sites
142(1)
Problems
143(10)
Appendix 4A: Performance Characteristics of Two-Level Memories
145(8)
External Memory
153(28)
Magnetic Disk
155(8)
RAID
163(9)
Optical Memory
172(5)
Magnetic Tape
177(1)
Recommended Reading and Web Sites
178(1)
Problems
179(2)
Input/Output
181(46)
External Devices
184(4)
I/O Modules
188(3)
Programmed I/O
191(4)
Interrupt-Driven I/O
195(8)
Direct Memory Access
203(4)
I/O Channels and Processors
207(2)
The External Interface: SCSI and Fire Wire
209(14)
Recommended Reading and Web Sites
223(1)
Problems
224(3)
Operating System Support
227(44)
Operating System Overview
229(12)
Scheduling
241(6)
Memory Management
247(12)
Pentium II and PowerPC Memory Management
259(9)
Recommended Reading and Web Sites
268(1)
Problems
269(2)
PART III THE CENTRAL PROCESSING UNIT 271(280)
Computer Arithmetic
273(50)
The Arithmetic and Logic Unit (ALU)
275(1)
Integer Representation
276(6)
Integer Arithmetic
282(16)
Floating-Point Representation
298(7)
Floating-Point Arithmetic
305(9)
Recommended Reading and Web Sites
314(1)
Problems
315(8)
Appendix 8A: Number Systems
317(6)
Instruction Sets: Characteristics and Functions
323(50)
Machine Instruction Characteristics
325(6)
Types of Operands
331(2)
Pentium II and PowerPC Data Types
333(3)
Types of Operations
336(13)
Pentium II and PowerPC Operation Types
349(9)
Assembly Language
358(2)
Recommended Reading
360(1)
Problems
360(13)
Appendix 9A: Stacks
364(4)
Appendix 9B: Little-, Big-, and Bi-Endian
368(5)
Instruction Sets: Addressing Modes and Formats
373(32)
Addressing
375(7)
Pentium and PowerPC Addressing Modes
382(6)
Instruction Formats
388(9)
Pentium and PowerPC Instruction Formats
397(5)
Recommended Reading
402(1)
Problems
402(3)
CPU Structure and Function
405(50)
Processor Organization
407(2)
Register Organization
409(5)
The Instruction Cycle
414(5)
Instruction Pipelining
419(15)
The Pentium Processor
434(9)
The PowerPC Processor
443(7)
Recommended Reading
450(1)
Problems
451(4)
Reduced Instruction Set Computers
455(44)
Instruction Execution Characteristics
458(4)
The Use of a Large Register File
462(5)
Compiler-Based Register Optimization
467(2)
Reduced Instruction Set Architecture
469(7)
RISC Pipelining
476(4)
MIPS R4000
480(8)
SPARC
488(6)
The RISC versus CISC Controversy
494(1)
Recommended Reading
495(1)
Problems
496(3)
Instruction-Level Parallelism and Superscalar Processors
499(52)
Overview
501(5)
Design Issues
506(9)
Pentium II
515(6)
PowerPC
521(8)
MIPS R10000
529(2)
UltraSPARC-II
531(3)
IA-64/Merced
534(11)
Recommended Reading
545(1)
Problems
546(5)
PART IV THE CONTROL UNIT 551(68)
Control Unit Operation
553(24)
Micro-operations
555(6)
Control of the Processor
561(12)
Hardwired Implementation
573(2)
Recommended Reading
575(1)
Problems
576(1)
Microprogrammed Control
577(42)
Basic Concepts
579(9)
Microinstruction Sequencing
588(5)
Microinstruction Execution
593(12)
TI 8800
605(10)
Applications of Microprogramming
615(1)
Recommended Reading
616(1)
Problems
617(2)
PART V PARALLEL ORGANIZATION 619(50)
Parallel Processing
621(48)
Multiple Processor Organizations
623(2)
Symmetric Multiprocessors
625(10)
Cache Coherence and the MESI Protocol
635(7)
Clusters
642(4)
Nonuniform Memory Access
646(4)
Vector Computation
650(13)
Recommended Reading
663(1)
Problems
664(5)
Appendix A Digital Logic 669(40)
A.1 Boolean Algebra
670(2)
A.2 Gates
672(3)
A.3 Combinational Circuits
675(21)
A.4 Sequential Circuits
696(11)
A.5 Problems
707(2)
Appendix B Projects for Teaching Computer Organization and Architecture 709(4)
B.1 Research Projects
710(1)
B.2 Simulation Projects
710(2)
B.3 Reading/Report Assignments
712(1)
Glossary 713(12)
References 725(14)
Index 739


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