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Computer Organization and Architecture : Designing for Performance,9780136073734
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Computer Organization and Architecture : Designing for Performance

by
Edition:
8th
ISBN13:

9780136073734

ISBN10:
0136073735
Format:
Hardcover
Pub. Date:
1/1/2010
Publisher(s):
Prentice Hall
List Price: $163.80

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    Computer Organization and Architecture : Designing for Performance





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iloverenting  March 8, 2011
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This is a very detailed book. I would not have made it through my class this semester without it. Also the best thing about this book is the cheap price I rented it for. Saved me a lot of money!






Computer Organization and Architecture : Designing for Performance: 5 out of 5 stars based on 1 user reviews.

Summary

KEY BENEFIT : Learn the fundamentals of processor and computer design from the newest edition of this award winning text. KEY TOPICS : Introduction; Computer Evolution and Performance; A Top-Level View of Computer Function and Interconnection; Cache Memory; Internal Memory Technology; External Memory; I/O; Operating System Support; Computer Arithmetic; Instruction Sets: Characteristics and Functions; Instruction Sets: Addressing Modes and Formats; CPU Structure and Function; RISCs; Instruction-Level Parallelism and Superscalar Processors; Control Unit Operation; Microprogrammed Control; Parallel Processing; Multicore Architecture. Online Chapters: Number Systems; Digital Logic; Assembly Language, Assemblers, and Compilers; The IA-64 Architecture. MARKET : Ideal for professionals in computer science, computer engineering, and electrical engineering.

Table of Contents

Web Site for the Bookp. iv
About the Authorp. xi
Prefacep. xiii
Reader's Guidep. 1
Outline of the Bookp. 2
A Roadmap for Readers and Instructorsp. 2
Why Study Computer Organization and Architecturep. 3
Internet and Web Resourcesp. 4
Overviewp. 7
Introductionp. 8
Organization and Architecturep. 9
Structure and Functionp. 10
Key Terms and Review Questionsp. 15
Computer Evolution and Performancep. 16
A Brief History of Computersp. 17
Designing for Performancep. 38
The Evolution of the Intel x86 Architecturep. 44
Embedded Systems and the ARMp. 46
Performance Assessmentp. 50
Recommended Reading and Web Sitesp. 57
Key Terms, Review Questions, and Problemsp. 59
The Computer Systemp. 63
A Top-Level View of Computer Function and Interconnectionp. 65
Computer Componentsp. 66
Computer Functionp. 68
Interconnection Structuresp. 83
Bus Interconnectionp. 85
PCIp. 95
Recommended Reading and Web Sitesp. 104
Key Terms, Review Questions, and Problemsp. 104
Appendix 3A Timing Diagramsp. 108
Cache Memoryp. 110
Computer Memory System Overviewp. 111
Cache Memory Principlesp. 118
Elements of Cache Designp. 121
Pentium 4 Cache Organizationp. 140
ARM Cache Organizationp. 143
Recommended Readingp. 145
Key Terms, Review Questions, and Problemsp. 146
Appendix 4A Performance Characteristics of Two-Level Memoriesp. 151
Internal Memory Technologyp. 158
Semiconductor Main Memoryp. 159
Error Correctionp. 169
Advanced DRAM Organizationp. 173
Recommended Reading and Web Sitesp. 179
Key Terms, Review Questions, and Problemsp. 180
External Memoryp. 184
Magnetic Diskp. 185
RAIDp. 194
Optical Memoryp. 203
Magnetic Tapep. 210
Recommended Reading and Web Sitesp. 212
Key Terms, Review Questions, and Problemsp. 214
Input/Outputp. 217
External Devicesp. 219
I/O Modulesp. 222
Programmed I/Op. 224
Interrupt-Driven I/Op. 228
Direct Memory Accessp. 236
I/O Channels and Processorsp. 242
The External Interface: Fire Wire and Infinibandp. 244
Recommended Reading and Web Sitesp. 253
Key Terms, Review Questions, and Problemsp. 254
Operating System Supportp. 259
Operating System Overviewp. 260
Schedulingp. 271
Memory Managementp. 277
Pentium Memory Managementp. 288
ARM Memory Managementp. 293
Recommended Reading and Web Sitesp. 298
Key Terms, Review Questions, and Problemsp. 299
The Central Processing Unitp. 303
Computer Arithmeticp. 305
The Arithmetic and Logic Unit (ALU)p. 306
Integer Representationp. 307
Integer Arithmeticp. 312
Floating-Point Representationp. 327
Floating-Point Arithmeticp. 334
Recommended Reading and Web Sitesp. 342
Key Terms, Review Questions, and Problemsp. 344
Instruction Sets: Characteristics and Functionsp. 348
Machine Instruction Characteristics and Functionsp. 348
Types of Operandsp. 356
Intel x86 and ARM Data Typesp. 358
Types of Operationsp. 362
Intel x86 and ARM Operation Typesp. 374
Recommended Readingp. 384
Key Terms, Review Questions, and Problemsp. 385
Appendix 10A Stacksp. 390
Appendix 10B Little, Big, and Bi-Endianp. 396
Instruction Sets: Addressing Modes and Formatsp. 400
Addressingp. 401
x86 and ARM Addressing Modesp. 408
Instruction Formatsp. 413
x86 and ARM Instruction Formatsp. 421
Assembly Languagep. 426
Recommended Readingp. 428
Key Terms, Review Questions, and Problemsp. 428
Processor Structure and Functionp. 432
Processor Organizationp. 433
Register Organizationp. 435
The Instruction Cyclep. 440
Instruction Pipeliningp. 444
The x86 Processor Familyp. 461
The ARM Processorp. 469
Recommended Readingp. 475
Key Terms, Review Questions, and Problemsp. 476
Reduced Instruction Set Computers (RISCs)p. 480
Instruction Execution Characteristicsp. 482
The Use of a Large Register Filep. 487
Compiler-Based Register Optimizationp. 492
Reduced Instruction Set Architecturep. 494
RISC Pipeliningp. 500
MIPS R4000p. 504
SPARCp. 511
The RISC versus CISC Controversyp. 517
Recommended Readingp. 518
Key Terms, Review Questions, and Problemsp. 518
Instruction-Level Parallelism and Superscalar Processorsp. 522
Overviewp. 524
Design Issuesp. 528
Pentium 4p. 538
ARM Cortex-A8p. 544
Recommended Readingp. 552
Key Terms, Review Questions, and Problemsp. 554
The Control Unitp. 559
Control Unit Operationp. 561
Micro-operationsp. 563
Control of the Processorp. 569
Hardwired Implementationp. 581
Recommended Readingp. 584
Key Terms, Review Questions, and Problemsp. 584
Microprogrammed Controlp. 586
Basic Conceptsp. 587
Microinstruction Sequencingp. 596
Microinstruction Executionp. 602
TI 8800p. 614
Recommended Readingp. 624
Key Terms, Review Questions, and Problemsp. 625
Parallel Organizationp. 627
Parallel Processingp. 628
The Use of Multiple Processorsp. 630
Symmetric Multiprocessorsp. 632
Cache Coherence and the MESI Protocolp. 640
Multithreading and Chip Multiprocessorsp. 646
Clustersp. 653
Nonuniform Memory Access Computersp. 660
Vector Computationp. 664
Recommended Reading and Web Sitesp. 676
Key Terms, Review Questions, and Problemsp. 677
Multicore Computersp. 684
Hardware Performance Issuesp. 685
Software Performance Issuesp. 690
Multicore Organizationp. 694
Intel x86 Multicore Organizationp. 696
ARM11 MPCorep. 699
Recommended Reading and Web Sitesp. 704
Key Terms, Review Questions, and Problemsp. 705
Projects for Teaching Computer Organization and Architecturep. 707
Interactive Simulationsp. 708
Research Projectsp. 708
Simulation Projectsp. 710
Assembly Language Projectsp. 711
Reading/Report Assignmentsp. 711
Writing Assignmentsp. 712
Test Bankp. 712
Assembly Language and Related Topicsp. 713
Assembly Languagep. 714
Assemblersp. 723
Loading and Linkingp. 728
Recommended Reading and Web Sitesp. 735
Key Terms, Review Questions, and Problemsp. 736
Online Chapters WilliamStalling.com/COA/COA8e.html
Number Systems 19-1
The Decimal System 19-2
The Binary System 19-2
Converting between Binary and Decimal 19-3
Hexadecimal Notation 19-5
Key Terms, Review Questions, and Problems 19-8
Digital Logic 20-1
Boolean Algebra 20-2
Gates 20-4
Combinational Circuits 20-7
Sequential Circuits 20-24
Programmable Logic Devices 20-33
Recommended Reading and Web Site 20-38
Key Terms and Problems 20-39
The IA-64 Architecture 21-1
Motivation 21-3
General Organization 21-4
Predication, Speculation, and Software Pipelining 21-6
IA-64 Instruction Set Architecture 21-23
Itanium Organization 21-28
Recommended Reading and Web Sites 21-31
Key Terms, Review Questions, and Problems 21-32
Online Appendices William Stallings.com/COA/COA8e.html
Hash Tables
Victim Cache Strategies
Victim Cache
Selective Victim Cache
Interleaved Memory
International Reference Alphabet
Virtual Memory Page Replacement Algorithms
Recursive Procedures
Recursion
Activation Tree Representation
Stack Processing
Recursion and Iteration
Additional Instruction Pipeline Topics
Pipeline Reservation Tables
Reorder Buffers
Scoreboarding
Tomasulo's Algorithm
Linear Tape Open Technology
DDR SDRAM
Glossaryp. 740
Referencesp. 750
Indexp. 763
Table of Contents provided by Ingram. All Rights Reserved.


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