Preface 

xiii  


1  (32) 


2  (6) 


2  (2) 


4  (2) 

Contemporary Logic Design 


6  (2) 

A Brief History of Logic Design 


8  (1) 


9  (6) 

Switches, Relays, and Circuits 


10  (2) 


12  (1) 


13  (1) 


14  (1) 


15  (18) 


25  (2) 


27  (1) 


28  (5) 


33  (60) 

Outputs as a Function of Inputs 


34  (3) 

Combinational Logic Defined 


34  (1) 

Examples of Combinational Logic 


34  (3) 

Laws and Theorems of Boolean Logic 


37  (9) 

Axioms of Boolean Algebra 


39  (3) 

Theorems of Boolean Algebra 


42  (3) 

Duality and DeMorgan's Law 


45  (1) 

Realizing Boolean Formulas 


46  (10) 


46  (3) 

Logic Blocks and Hierarchy 


49  (1) 

Time Behavior and Waveforms 


50  (2) 

Minimizing the Number of Gates and Wires 


52  (2) 

Case Study: 7Segment Decoder 


54  (2) 


56  (9) 


56  (7) 

Incompletely Specified Functions 


63  (2) 

Motivation for TwoLevel Simplification 


65  (11) 

Graphing Boolean Expressions 


66  (1) 


67  (2) 


69  (7) 


76  (4) 

Motivation for Multilevel Minimization 


80  (13) 


80  (1) 

Criteria for Multilevel Simplification 


81  (2) 


83  (1) 


84  (1) 


85  (8) 

Working with Combinational Logic 


93  (62) 


93  (10) 

Formalizing the Process of Boolean Minimization 


99  (3) 

KMaps Revisited: Five and SixVariable Functions 


102  (1) 

Automating TwoLevel Simplification 


103  (11) 


104  (4) 


108  (3) 

Realizing SoP and PoS Logic Networks 


111  (3) 

Multilevel Simplification 


114  (8) 

Automating Multilevel Simplification 


122  (7) 

Multilevel Logic Optimization Scripts 


122  (4) 

Realizing Multilevel Logic Networks 


126  (3) 

Time Response in Combinational Networks 


129  (10) 


129  (1) 


130  (1) 

Analysis of a PulseShaper Circuit 


131  (1) 


132  (1) 

Hazard Detection and Elimination in TwoLevel Networks 


133  (3) 

Static Hazards in Multilevel Networks 


136  (1) 

Designing Static HazardFree Multilevel Circuits 


137  (1) 


138  (1) 

Hardware Description Languages 


139  (16) 


141  (1) 


141  (2) 


143  (1) 


143  (3) 


146  (1) 


146  (1) 


147  (8) 

Combinational Logic Technologies 


155  (66) 


156  (8) 

From Switches to Integrated Circuits 


156  (2) 

Packaged Logic, Configurability, and Programmable Logic 


158  (4) 


162  (2) 


164  (32) 


164  (4) 


168  (11) 


179  (17) 

TwoLevel and Multilevel Logic 


196  (9) 


205  (16) 


206  (4) 

OpenCollector Outputs and Wired Logic 


210  (2) 


212  (1) 


213  (1) 


213  (8) 

Case Studies in Combinational Logic Design 


221  (38) 


222  (2) 

A Simple Process LineControl Problem 


224  (3) 


227  (4) 


231  (3) 


234  (4) 


238  (8) 


238  (2) 


240  (4) 


244  (1) 


245  (1) 

Arithmetic Logic Unit Design 


246  (3) 


247  (2) 


249  (10) 


253  (1) 


253  (1) 


254  (5) 


259  (48) 

Sequential Logic Elements 


260  (18) 

Simple Circuits with Feedback 


260  (5) 


265  (2) 


267  (1) 


268  (2) 

MasterSlave Latches and EdgeTriggered FlipFlops 


270  (3) 


273  (5) 


278  (11) 

Cascaded FlipFlops and Setup/Hold/Propagation 


279  (2) 


281  (1) 


282  (2) 

Metastability and Synchronizer Failure 


284  (1) 

Selftimed and Speedindependent Circuits 


285  (4) 


289  (6) 


289  (2) 


291  (4) 

Hardware Description Languages 


295  (12) 


298  (1) 


299  (1) 


300  (7) 


307  (48) 


308  (13) 


310  (2) 

Counters with More Complex Sequencing 


312  (2) 


314  (2) 


316  (1) 


316  (5) 

The Concept of the State Machine 


321  (5) 

Odd or Even Parity Checker 


321  (3) 


324  (2) 

Basic FSM Design Approach 


326  (13) 

Finite State Machine Design Procedure 


327  (5) 


332  (1) 

State Diagram Representation 


333  (1) 

Comparison of the Two Machine Types 


334  (5) 

Motivation for Optimization 


339  (16) 

Two State Diagrams, Same I/O Behavior 


339  (1) 

Advantages of Minimum States 


340  (1) 

State, Input, and Output Encoding 


341  (1) 


342  (1) 

A TrafficLight Controller 


342  (4) 


346  (1) 


347  (1) 


348  (7) 

Working with Finite State Machines 


355  (46) 

State Minimization/Reduction 


356  (11) 


356  (4) 


360  (5) 

Equivalent States in the Presence of Don't Cares 


365  (1) 

When State Minimization Doesn't Help 


366  (1) 


367  (13) 


369  (1) 


370  (1) 


371  (1) 


372  (2) 


374  (6) 

Finite State Machine Partitioning 


380  (6) 

Finite State Machine Partitioning by Introducing Idle States 


381  (5) 

Hardware Description Languages 


386  (15) 


391  (1) 


392  (1) 


392  (9) 

Sequential Logic Technologies 


401  (51) 

Basic Sequential Logic Components 


402  (4) 


406  (3) 

FSM Design with Programmable Logic 


409  (12) 

Mapping a State Machine into a ROM Implementation 


409  (1) 

ROM Versus PLABased Design 


410  (5) 

Alternative PAL Architectures 


415  (6) 

FSM Design with More Sophisticated Programmable Logic Devices 


421  (18) 

PLDs: Programmable Logic Devices 


422  (1) 

Altera Erasable Programmable Logic Devices 


422  (7) 

Actel FieldProgrammable Gate Arrays 


429  (3) 

Xilinx Field Programmable Gate Arrays 


432  (7) 

Case Study: TrafficLight Controller 


439  (13) 

Problem Decomposition: TrafficLight State Machine 


439  (3) 

PLA/PAL/ROMBased Implementation 


442  (1) 

CounterBased Implementation 


443  (2) 

FPGABased Implementation 


445  (1) 


446  (1) 


447  (1) 


447  (5) 

Case Studies in Sequential Logic Design 


452  (57) 

A Finite String Recognizer 


452  (8) 


460  (3) 

A Digital Combination Lock 


463  (4) 


467  (15) 

RAM Basics: A 1024 x 4Bit Static RAM 


467  (3) 


470  (4) 


474  (1) 


475  (2) 

Design of a Simple Memory Controller 


477  (5) 


482  (5) 

A Serial Line Transmitter/Receiver 


487  (22) 


499  (1) 


499  (1) 


500  (9) 


509  (2) 

Appendix A Number Systems 


511  (22) 

Positional Number Notation 


511  (2) 


511  (1) 

Binary, Octal, and Hexadecimal Numbers 


512  (1) 

Conversion Between Binary, Octal, and Hexadecimal Systems 


513  (3) 

Conversion from Binary to Octal or Hexadecimal 


513  (1) 

Conversion from Octal to Hexadecimal and Vice Versa 


514  (1) 

Conversion from Base 10 to Base 2: Successive Division 


514  (2) 

Binary Arithmetic Operations 


516  (4) 

Addition in Positional Notation 


516  (2) 

Subtraction in Positional Notation 


518  (2) 

Representation of Negative Numbers 


520  (7) 


520  (1) 


521  (1) 


522  (2) 

Addition and Subtraction of Numbers 


524  (2) 


526  (1) 

BCD Number Representation 


527  (6) 


528  (1) 


529  (4) 

Appendix B Basic Electronics 


533  (33) 


533  (3) 


533  (1) 

Fundamental Quantities and Laws 


534  (2) 

Logic Gates from Resistors and Diodes 


536  (2) 


536  (1) 


537  (1) 


538  (5) 

Basic BipolarTransistor Logic 


539  (1) 


539  (2) 

TransistorTransistor Logic 


541  (1) 

TTL Circuits and Noise Margin 


542  (1) 


543  (11) 

VoltageControlled Switches 


543  (1) 

Logic Gates from MOS Switches 


544  (2) 


546  (1) 

Switch and Steering Logic 


547  (7) 

Elements of the Data Sheet 


554  (2) 

Simple Performance Calculations 


556  (1) 

Schematic Documentation Standards 


556  (4) 

Practical Aspects of Inputs, Outputs, and Clocks 


560  (6) 

Switches and LEDs as Inputs and Outputs 


561  (1) 


562  (2) 


564  (1) 


565  (1) 

Appendix C FlipFlop Types 


566  (13) 


566  (2) 

Realizing Circuits with Different Kinds of FlipFlops 


568  (2) 

Conversion of One FlipFlop Type to Another 


568  (2) 

Shift Registers and Counters 


570  (9) 

Implementation with RS FlipFlops 


572  (2) 

Implementation with JK FlipFlops 


574  (2) 

Implementation with T FlipFlops 


576  (1) 

Implementation with D FlipFlops 


576  (2) 


578  (1) 
Appendix Review 

579  (1) 
Exercises 

579  (2) 
Index 

581  