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Digital Design,9780131989245
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Digital Design

by ;
Edition:
4th
ISBN13:

9780131989245

ISBN10:
0131989243
Format:
Hardcover w/Disk
Pub. Date:
1/1/2007
Publisher(s):
Prentice Hall
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Summary

For sophomore courses on digital design in an Electrical Engineering, Computer Engineering, or Computer Science department. Digital Design, fourth edition is a modern update of the classic authoritative text on digital design. This book teaches the basic concepts of digital design in a clear, accessible manner. The book presents the basic tools for the design of digital circuits and provides procedures suitable for a variety of digital applications.

Table of Contents

Prefacep. ix
Digital Systems and Binary Numbersp. 1
Digital Systemsp. 1
Binary Numbersp. 3
Number-Base Conversionsp. 5
Octal and Hexadecimal Numbersp. 8
Complementsp. 9
Signed Binary Numbersp. 14
Binary Codesp. 17
Binary Storage and Registersp. 25
Binary Logicp. 28
Boolean Algebra and Logic Gatesp. 36
Introductionp. 36
Basic Definitionsp. 36
Axiomatic Definition of Boolean Algebrap. 38
Basic Theorems and Properties of Boolean Algebrap. 41
Boolean Functionsp. 44
Canonical and Standard Formsp. 48
Other Logic Operationsp. 55
Digital Logic Gatesp. 57
Integrated Circuitsp. 63
Gate-Level Minimizationp. 70
Introductionp. 70
The Map Methodp. 70
Four-Variable Mapp. 76
Five-Variable Mapp. 81
Product-of-Sums Simplificationp. 83
Don't-Care Conditionsp. 86
NAND and NOR Implementationp. 89
Other Two-Level Implementationsp. 96
Exclusive-OR Functionp. 101
Hardware Description Languagep. 106
Combinational Logicp. 122
Introductionp. 122
Combinational Circuitsp. 122
Analysis Procedurep. 123
Design Procedurep. 126
Binary Adder-Subtractorp. 130
Decimal Adderp. 139
Binary Multiplierp. 142
Magnitude Comparatorp. 144
Decodersp. 146
Encodersp. 150
Multiplexersp. 152
HDL Models of Combinational Circuitsp. 159
Synchronous Sequential Logicp. 182
Introductionp. 182
Sequential Circuitsp. 182
Storage Elements: Latchesp. 184
Storage Elements: Flip-Flopsp. 188
Analysis of Clocked Sequential Circuitsp. 195
Synthesizable HDL Models of Sequential Circuitsp. 207
State Reduction and Assignmentp. 227
Design Procedurep. 225
Registers and Countersp. 242
Registersp. 242
Shift Registersp. 245
Ripple Countersp. 253
Synchronous Countersp. 258
Other Countersp. 265
HDL for Registers and Countersp. 269
Memory and Programmable Logicp. 284
Introductionp. 284
Random-Access Memoryp. 285
Memory Decodingp. 291
Error Detection and Correctionp. 296
Read-Only Memoryp. 299
Programmable Logic Arrayp. 305
Programmable Array Logicp. 309
Sequential Programmable Devicesp. 311
Design at the Register Transfer Levelp. 334
Introductionp. 334
Register Transfer Level (RTL) Notationp. 334
Register Transfer Level in HDLp. 336
Algorithmic State Machines (ASMs)p. 345
Design Examplep. 352
HDL Description of Design Examplep. 367
Sequential Binary Multiplierp. 371
Control Logicp. 376
HDL Description of Binary Multiplierp. 382
Design with Multiplexersp. 390
Race-Free Designp. 407
Latch-Free Designp. 403
Other Language Featuresp. 404
Asynchronous Sequential Logicp. 415
Introductionp. 415
Analysis Procedurep. 477
Circuits with Latchesp. 425
Design Procedurep. 433
Reduction of State and Flow Tablesp. 439
Race-Free State Assignmentp. 446
Hazardsp. 452
Design Examplep. 457
Digital Integrated Circuitsp. 471
Introductionp. 471
Special Characteristicsp. 473
Bipolar-Transistor Characteristicsp. 477
RTL and DTL Circuitsp. 481
Transistor-Transistor Logicp. 484
Emitter-Coupled Logicp. 493
Metal-Oxide Semiconductorp. 495
Complementary MOSp. 498
CMOS Transmission Gate Circuitsp. 501
Switch-Level Modeling with HDLp. 505
Laboratory Experiments with Standard ICs and FPGAs 57p. 511
Introduction to Experimentsp. 511
Experiment 1: Binary and Decimal Numbersp. 516
Experiment 2: Digital Logic Gatesp. 579
Experiment 3: Simplification of Boolean Functionsp. 520
Experiment 4: Combinational Circuitsp. 522
Experiment 5: Code Convertersp. 524
Experiment 6: Design with Multiplexersp. 526
Experiment 7: Adders and Subtractorsp. 527
Experiment 8: Flip-Flopsp. 550
Experiment 9: Sequential Circuitsp. 532
Experiment 10: Countersp. 534
Experiment 11: Shift Registersp. 535
Experiment 12: Serial Additionp. 538
Experiment 13: Memory Unitp. 539
Experiment 14: Lamp Handballp. 547
Experiment 15: Clock-Pulse Generatorp. 545
Experiment 16: Parallel Adder and Accumulatorp. 547
Experiment 17: Binary Multiplierp. 549
Experiment 18: Asynchronous Sequential Circuitsp. 553
Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAsp. 553
Standard Graphic Symbolsp. 589
Rectangular-Shape Symbolsp. 559
Qualifying Symbolsp. 562
Dependency Notationp. 564
Symbols for Combinational Elementsp. 566
Symbols for Flip-Flopsp. 550
Symbols for Registersp. 570
Symbols for Countersp. 573
Symbol for RAMp. 575
Answers to Selected Problemsp. 577
Indexp. 597
Table of Contents provided by Ingram. All Rights Reserved.


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