Preface 

xix  
How to Use This Book for SelfStudy 

xxiii  

Introduction Number Systems and Conversion 


1  (25) 


1  (1) 


2  (4) 

Digital Systems and Switching Circuits 


6  (2) 

Number Systems and Conversion 


8  (4) 


12  (3) 

Representation of Negative Numbers 


15  (5) 

Addition of 2's Complement Numbers 


17  (1) 

Addition of 1's Complement Numbers 


18  (2) 


20  (6) 


23  (3) 


26  (27) 


26  (1) 


27  (6) 


33  (1) 


34  (2) 

Boolean Expressions and Truth Tables 


36  (2) 


38  (1) 

Commutative, Associative, and Distributive Laws 


39  (2) 


41  (2) 

Multiplying Out and Factoring 


43  (2) 


45  (8) 


47  (5) 

Laws and Theorems of Boolean Algebra 


52  (1) 

Boolean Algebra (Continued) 


53  (24) 


53  (1) 


54  (4) 

Multiplying Out and Factoring Expressions 


58  (2) 

ExclusiveOR and Equivalence Operations 


60  (2) 


62  (2) 

Algebraic Simplification of Switching Expressions 


64  (2) 

Proving the Validity of an Equation 


66  (11) 


68  (6) 


74  (3) 

Applications of Boolean Algebra Minterm and Maxterm Expansions 


77  (32) 


77  (1) 


78  (6) 

Conversion of English Sentences to Boolean Equations 


84  (2) 

Combinational Logic Design Using a Truth Table 


86  (1) 

Minterm and Maxterm Expansions 


87  (3) 

General Minterm and Maxterm Expansions 


90  (3) 

Incompletely Specified Functions 


93  (1) 

Examples of Truth Table Construction 


94  (4) 

Design of Binary Adders and Subtracters 


98  (11) 


101  (8) 


109  (40) 


109  (1) 


110  (10) 

Minimum Forms of Switching Functions 


120  (1) 

Two and ThreeVariable Karnaugh Maps 


121  (5) 

FourVariable Karnaugh Maps 


126  (3) 

Determination of Minimum Expressions Using Essential Prime Implicants 


129  (5) 

FiveVariable Karnaugh Maps 


134  (2) 

Other Uses of Karnaugh Maps 


136  (2) 

Other Forms of Karnaugh Maps 


138  (11) 


139  (5) 


144  (5) 


149  (24) 


149  (1) 


150  (5) 

Determination of Prime Implicants 


155  (3) 

The Prime Implicant Chart 


158  (3) 


161  (1) 

Simplification of Incompletely Specified Functions 


162  (1) 

Simplification Using MapEntered Variables 


163  (2) 


165  (8) 


166  (4) 


170  (3) 

MultiLevel Gate Circuits NAND and NOR Gates 


173  (28) 


173  (1) 


174  (5) 

MultiLevel Gate Circuits 


179  (4) 


183  (2) 

Design of TwoLevel Circuits Using NAND and NOR Gates 


185  (3) 

Design of MultiLevel NAND and NOR Gate Circuits 


188  (1) 

Circuit Conversion Using Alternative Gate Symbols 


189  (3) 

Design of TwoLevel, MultipleOutput Circuits 


192  (4) 

Determination of Essential Prime Implicants for MultipleOutput Realization 


194  (2) 

MultipleOutput NAND and NOR Circuits 


196  (5) 


196  (5) 

Combinational Circuit Design and Simulation Using Gates 


201  (23) 


201  (1) 


202  (3) 

Review of Combinational Circuit Design 


205  (1) 

Design of Circuits with Limited Gate FanIn 


206  (2) 

Gate Delays and Timing Diagrams 


208  (2) 

Hazards in Combinational Logic 


210  (3) 

Simulation and Testing of Logic Circuits 


213  (11) 


216  (2) 


218  (6) 

Multiplexers, Decoders, and Programmable Logic Devices 


224  (33) 


224  (1) 


225  (5) 


230  (1) 


230  (3) 


233  (2) 


235  (3) 


238  (4) 

Programmable Logic Devices 


242  (5) 

Programmable Logic Arrays 


242  (3) 


245  (2) 

Complex Programmable Logic Devices 


247  (2) 

Field Programmable Gate Arrays 


249  (8) 

Decomposition of Switching Functions 


250  (3) 


253  (4) 


257  (33) 


257  (1) 


258  (4) 

VHDL Description of Combinational Circuits 


262  (3) 

VHDL Models for Multiplexers 


265  (2) 


267  (5) 


269  (3) 


272  (1) 


273  (3) 


276  (1) 


277  (2) 


279  (3) 

Compilation and Simulation of VHDL Code 


282  (8) 


283  (7) 


290  (29) 


290  (1) 


291  (4) 


295  (1) 


296  (4) 


300  (1) 

EdgeTriggered D FlipFlop 


301  (2) 


303  (2) 


305  (1) 


306  (1) 

FlipFlops with Additional Inputs 


307  (2) 


309  (10) 


310  (6) 


316  (3) 


319  (36) 


319  (1) 


320  (5) 

Registers and Register Transfers 


325  (4) 

Parallel Adder with Accumulator 


327  (2) 


329  (4) 

Design of Binary Counters 


333  (5) 

Counters for Other Sequences 


338  (4) 

Counter Design Using D FlipFlops 


341  (1) 

Counter Design Using SR and JK FlipFlops 


342  (3) 

Derivation of FlipFlop Input EquationsSummary 


345  (10) 


349  (6) 

Analysis of Clocked Sequential Circuits 


355  (35) 


355  (1) 


356  (6) 

A Sequential Parity Checker 


362  (2) 

Analysis by Signal Tracing and Timing Charts 


364  (3) 


367  (7) 

Construction and Interpretation of Timing Charts 


372  (2) 

General Models for Sequential Circuits 


374  (16) 


378  (4) 


382  (8) 

Derivation of State Graphs and Tables 


390  (35) 


390  (1) 


391  (2) 

Design of a Sequence Detector 


393  (5) 

More Complex Design Problems 


398  (4) 

Guidelines for Construction of State Graphs 


402  (5) 

Serial Data Code Conversion 


407  (3) 

Alphanumeric State Graph Notation 


410  (15) 


412  (7) 


419  (6) 

Reduction of State Tables State Assignment 


425  (40) 


425  (1) 


426  (7) 

Elimination of Redundant States 


433  (1) 


434  (3) 

Determination of State Equivalence Using an Implication Table 


437  (3) 

Equivalent Sequential Circuits 


440  (2) 

Incompletely Specified State Tables 


442  (1) 

Derivation of FlipFlop Input Equations 


443  (3) 

Equivalent State Assignments 


446  (3) 

Guidelines for State Assignment 


449  (4) 

Using a OneHot State Assignment 


453  (12) 


455  (10) 

Sequential Circuit Design 


465  (36) 


465  (1) 


466  (2) 

Summary of Design Procedure for Sequential Circuits 


468  (1) 

Design ExampleCode Converter 


469  (3) 

Design of Iterative Circuits 


472  (4) 


473  (3) 

Design of Sequential Circuits Using ROMs and PLAs 


476  (3) 

Sequential Circuit Design Using CPLDs 


479  (4) 

Sequential Circuit Design Using FPGAs 


483  (2) 

Simulation and Testing of Sequential Circuits 


485  (5) 

Overview of ComputerAided Design 


490  (11) 


492  (6) 


498  (3) 

VHDL for Sequential Logic 


501  (34) 


501  (1) 


502  (4) 

Modeling FlipFlops Using VHDL Processes 


506  (3) 

Modeling Registers and Counters Using VHDL Processes 


509  (5) 

Modeling Combinational Logic Using VHDL Processes 


514  (1) 

Modeling a Sequential Machine 


515  (7) 


522  (3) 

More about Processes and Sequential Statements 


525  (10) 


527  (6) 


533  (2) 

Circuits for Arithmetic Operations 


535  (28) 


535  (1) 


536  (2) 

Serial Adder with Accumulator 


538  (4) 

Design of a Parallel Multiplier 


542  (4) 

Design of a Binary Divider 


546  (17) 


551  (4) 


555  (8) 

State Machine Design with SM Charts 


563  (20) 


563  (1) 


564  (1) 


565  (4) 


569  (6) 


575  (8) 


579  (4) 

VHDL for Digital System Design 


583  (27) 


583  (1) 


584  (3) 

VHDL Code for a Serial Adder 


587  (1) 

VHDL Code for a Binary Multiplier 


588  (11) 

VHDL Code for a Binary Divider 


599  (2) 

VHDL Code for a Dice Game Simulator 


601  (3) 


604  (6) 


605  (3) 


608  (2) 


610  (13) 


610  (6) 


616  (5) 


621  (2) 
References 

623  (1) 
Answers to Selected Study Guide Questions and Problems 

624  (57) 
Index 

681  