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| Introduction: Number Systems and Conversion | |
| Digital Systems and Switching Circuits | |
| Number Systems and Conversion | |
| Binary Arithmetic | |
| Representation of Negative Numbers | |
| Binary Codes | |
| Boolean Algebra | |
| Introduction | |
| Basic Operations | |
| Boolean Expressions and Truth Tables | |
| Basic Theorems | |
| Commutative, Associative, and Distributive Laws | |
| Simplification Theorems | |
| Multiplying Out and Factoring | |
| DeMorgan's Laws | |
| Boolean Algebra (Cont) | |
| Multiplying Out and Factoring Expressions | |
| Exclusive-OR and Equivalence Operations | |
| The Consensus Theorem | |
| Algebraic Simplification of Switching Expressions | |
| Proving Validity of an Equation | |
| Applications of Boolean Algebra: Minterm and Maxterm Expressions | |
| Conversion of English Sentences to Boolean Equations | |
| Combinational Logic Design Using a Truth Table | |
| Minterm and Maxterm Expansions | |
| General Minterm and Maxterm Expansions | |
| Incompletely Specified Functions | |
| Examples of Truth Table Construction | |
| Design of Binary Adders | |
| Karnaugh Maps | |
| Minimum Forms of Switching Functions | |
| Two- and Three-Variable Karnaugh Maps | |
| Four-Variable Karnaugh Maps | |
| Determination of Minimum Expressions Using Essential Prime Implicants | |
| Five-Variable Karnaugh Maps | |
| Other Uses of Karnaugh Maps | |
| Other Forms of Karnaugh Maps | |
| Quine-McClusky Method | |
| Determination of Prime Implicants | |
| The Prime Implicant Chart | |
| Petrick's Method | |
| Simplification of Incompletely Specified Functions | |
| Simplification Using Map-Entered Variables | |
| Conclusion | |
| Multi-Level Gate Circuits: NAND and NOR Gates Multi-Level Gate Circuits | |
| NAND and NOR Gates | |
| Design of Two-Level Circuits Using NAND and NOR Gates | |
| Design of Multi-Level NAND and NOR Gate Circuits | |
| Circuit Conversion Using Alternative Gate Symbols | |
| Design of Two-Level, Multiple-Output Circuits Determination of Essential Prime Implicants for Multiple-Output Realization | |
| Multiple-Output NAND and NOR Circuits | |
| Combinational Circuit Design and Simulation Using Gates Review of Combinational Circuit Design | |
| Design of Circuits with Limited Gate Fan-In | |
| Gate Delays and Timing Diagrams | |
| Hazards in Combinational Logic | |
| Simulation and Testing of Logic Circuits | |
| Multiplexers, Decodes, and Programmable Logic Devices Introduction | |
| Multiplexers | |
| Three-State Buffers | |
| Decoders and Encoders | |
| Read-Only Memories | |
| Programmable Logic Devices | |
| Complex Programmable Logic Devices | |
| Field Programmable Gate Arrays | |
| Introduction to VHDL VHDL Description of Combinational Circuits | |
| VHDL Models for Multiplexers | |
| VHDL Modules | |
| Signals and Constants | |
| Arrays | |
| VHDL Operators | |
| Packages and Libraries | |
| IEEE Standard Logic | |
| Compilation and Simulation of VHDL Code | |
| Latches and Flip-Flops Introduction | |
| Set-Reset Latch | |
| Gated D Latch | |
| Edge-Triggered D Flip-Flop | |
| S-R Flip-Flop | |
| J-K Flip-Flop | |
| T Flip-Flop | |
| Flip-Flops with Additional Inputs | |
| Summary | |
| Registers and Counters Registers and Register Transfers | |
| Shift Registers | |
| Design of Binary Counters | |
| Counters for Other Sequences | |
| Counter Design Using S-R and J-K Flip-XFlops | |
| Derivation of Flip-Flop Input Equations-Summary | |
| Analysis of Clocked Sequential Circuits A Sequential Parity Checker | |
| Analysis by Signal Tracing and Timing Charts | |
| State Tables and Graphs | |
| General Models for Sequential Circuits | |
| Derivation of State Graphs and Tables | |
| Design of a Sequence Detector | |
| More Complex Design Problems | |
| Guidelines for Construction of State Graphs | |
| Serial Data Code Conversion | |
| Alphanumeric State Graph Notation | |
| Reduction of State Tables State Assignment Elimination of Redundant States | |
| Equivalent States | |
| Determination of State Equivalence Using an Implication Table | |
| Equivalent Sequential Circuits | |
| Incompletely Specified State Tables | |
| Derivation of Flip-Flop Input Equations | |
| Equivalent State Assignments | |
| Guidelines for State Assignment | |
| Using a One-Hot State Assignment | |
| Sequential Circuit Design | |
| Summary of Design Procedure for Sequential Circuits | |
| Design Example-Code Converter | |
| Design of Iterative Circuits | |
| Design of Sequential Circuits Using ROMs and PLAs | |
| Sequential Circuit Design Using CPLDs | |
| Sequential Circuit Design Using FPGAs | |
| Simulation and Testing of Sequential Circuits | |
| Overview of Computer-Aided Design | |
| VHDL for Sequential Logic | |
| Modeling Flip-Flops Using VHDL Processes | |
| Modeling Registers and Counters Using VHDL Processes | |
| Modeling Combinational Logic Using VHDL Processes | |
| Modeling a Sequential Machine | |
| Synthesis of VHDL Code | |
| More About Processes and Sequential Statements | |
| Circuits for Arithmetic Operations | |
| Serial Adder with Accumulator | |
| Design of a Parallel Multiplier /Design of a Binary Divider | |
| State Machine Design with SM Charts State Machine Charts | |
| Derivation of SM Charts | |
| Realization of SM Charts | |
| VHDL for Digital System Design | |
| VHDL Code for a Serial Adder | |
| VHDL Code for a Binary Multiplier | |
| VHDL Code for a Binary Divider | |
| VHDL Code for a Dice Game Simulator | |
| Concluding Remarks | |
| Appendices MOS and CMOS Logic | |
| VHDL Language Summary /Proofs of Theorems | |
| References | |
| Answers to Selected Study Guide Questions and Problems | |
| Index | |
| Table of Contents provided by Publisher. All Rights Reserved. |
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