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Dr. Sandip Kundu is a professor in the Electrical and Computer Engineering Department at the University of Massachusetts at Amherst, specializing in semiconductor and lithographic manufacturing.
Dr. Aswin Sreedhar is a research assistant at the Electrical and Computer Engineering Department at the University of Massachusetts.
Preface | p. xiii |
Introduction | p. 1 |
Technology Trends: Extending Moore's Law | p. 1 |
Device Improvements | p. 3 |
Silicon on Insulator | p. 4 |
Multigate Devices | p. 5 |
Nanodevices | p. 6 |
Contributions from Material Science | p. 7 |
Low-K and High-K Dielectrics | p. 7 |
Strained Silicon | p. 9 |
Deep Subwavelength Lithography | p. 10 |
Mask Manipulation Techniques | p. 12 |
Increasing Numerical Aperture | p. 14 |
Design for Manufacturability | p. 15 |
Value and Economics of DFM | p. 15 |
Variabilities | p. 18 |
The Need for a Model-Based DFM Approach | p. 23 |
Design for Reliability | p. 23 |
Summary | p. 24 |
References | p. 25 |
Semiconductor Manufacturing | p. 27 |
Introduction | p. 27 |
Patterning Process | p. 28 |
Photolithography | p. 29 |
Resist Coat | p. 30 |
Preexposure (Soft) Bake | p. 30 |
Mask Alignment | p. 31 |
Exposure | p. 32 |
Postexposure Bake (PEB) | p. 32 |
Development | p. 32 |
Hard Bake | p. 33 |
Etching Techniques | p. 33 |
Wet Etching Techniques | p. 33 |
Dry Etching Techniques | p. 35 |
Optical Pattern Formation | p. 36 |
Illumination | p. 37 |
Diffraction | p. 40 |
Imaging Lens | p. 45 |
Exposure System | p. 47 |
Aerial Image and Reduction Imaging | p. 48 |
Resist Pattern Formation | p. 51 |
Partial Coherence | p. 53 |
Lithography Modeling | p. 55 |
Phenomenological Modeling | p. 56 |
Hopkins Approach to Partially Coherent Imaging | p. 56 |
Resist Diffusion | p. 57 |
Simplified Resist Model | p. 57 |
Sum-of-Coherent-Systems Approach | p. 58 |
Fully Physical Resist Modeling | p. 59 |
Summary | p. 60 |
References | p. 61 |
Process and Device Variability: Analysis and Modeling | p. 63 |
Introduction | p. 63 |
Gate Length Variation | p. 70 |
Patterning Variations Due to Photolithography | p. 70 |
Proximity Effects | p. 71 |
Defocus | p. 74 |
Lens Aberration | p. 75 |
Modeling Nonrectangular Gates (NRGs) | p. 80 |
Line Edge Roughness: Theory and Characterization | p. 82 |
Gate Width Variation | p. 87 |
Atomistic Fluctuations | p. 88 |
Thickness Variation in Metal and Dielectric | p. 91 |
Stress-Induced Variation | p. 96 |
Summary | p. 99 |
References | p. 99 |
Manufacturing-Aware Physical Design Closure | p. 103 |
Introduction | p. 103 |
Control of the Lithographic Process Window | p. 108 |
Resolution Enhancement Techniques | p. 113 |
Optical Proximity Correction | p. 114 |
Subresolution Assist Features | p. 118 |
Phase Shift Masking | p. 120 |
Off-Axis Illumination | p. 124 |
Physical Design for DFM | p. 126 |
Geometric Design Rules | p. 127 |
Restrictive Design Rules | p. 127 |
Model-Based Rules Check and Printability Verification | p. 129 |
Manufacturability-Aware Standard Cell Design | p. 131 |
Mitigating the Antenna Effect | p. 135 |
Placement and Routing for DFM | p. 138 |
Advanced Lithographic Techniques | p. 141 |
Double Patterning | p. 142 |
Inverse Lithography | p. 148 |
Other Advanced Techniques | p. 153 |
Summary | p. 153 |
References | p. 153 |
Metrology, Manufacturing Defects, and Defect Extraction | p. 157 |
Introduction | p. 157 |
Process-Induced Defects | p. 161 |
Classification of Error Sources | p. 162 |
Defect Interaction and Electrical Effects | p. 164 |
Modeling Particle Defects | p. 166 |
Defining Critical Area and Probability of Failure | p. 167 |
Critical Area Estimation | p. 169 |
Particulate Yield Models | p. 172 |
Layout Methods to Improve Critical Area | p. 173 |
Pattern-Dependent Defects | p. 175 |
Pattern-Dependent Defect Types | p. 176 |
Pattern Density Problems | p. 178 |
Statistical Approach to Modeling Patterning Defects | p. 179 |
Case Study: Yield Modeling and Enhancement for Optical Lithography | p. 179 |
Case Study: Linewidth-Based Yield When Considering Lithographic Variations | p. 181 |
Layout Methods That Mitigate Patterning Defects | p. 184 |
Metrology | p. 186 |
Precision and Tolerance in Measurement | p. 187 |
CD Metrology | p. 188 |
Scanning Electron Microscopy | p. 188 |
Electrical CD Measurement | p. 190 |
Scatterometry | p. 193 |
Overlay Metrology | p. 195 |
Other In-Line Measurements | p. 197 |
In-Sity Metrology | p. 198 |
Failure Analysis Techniques | p. 199 |
Nondestructive Techniques | p. 201 |
Failure Verification | p. 201 |
Optical Microscopy | p. 201 |
X-Ray Radiography | p. 202 |
Hermeticity Testing | p. 202 |
Particle Impact Noise Detection | p. 202 |
Destructive Techniques | p. 203 |
Microthermography | p. 203 |
Decapsulation | p. 203 |
Surface Analysis | p. 203 |
Summary | p. 204 |
References | p. 204 |
Defect Impact Modeling and Yield Improvement Techniques | p. 207 |
Introduction | p. 207 |
Modeling the Impact of Defects on Circuit Behavior | p. 209 |
Defect-Fault Relationship | p. 210 |
Role of Defect-Fault Models | p. 211 |
Defect-Based Fault Models | p. 212 |
Defect-Based Bridging Fault Model | p. 214 |
Abstract Fault Models | p. 215 |
Hybrid Fault Models | p. 218 |
Test Flow | p. 218 |
Yield Improvement | p. 221 |
Fault Tolerance | p. 222 |
Traditional Structural Redundancy Techniques | p. 222 |
Nonstructural Redundancy Techniques | p. 227 |
NAND Multiplexing | p. 230 |
Reconfiguration | p. 231 |
Comparison of Redundancy-Based Fault Tolerance Techniques | p. 232 |
Fuses | p. 233 |
Fault Avoidance | p. 235 |
Summary | p. 239 |
References | p. 241 |
Physical Design and Reliability | p. 243 |
Introduction | p. 243 |
Electromigration | p. 247 |
Hot Carrier Effects | p. 250 |
Hot Carrier Injection Mechanisms | p. 251 |
Device Damage Characteristics | p. 253 |
Time-Dependent Dielectric Breakdown | p. 254 |
Mitigating HCI-Induced Degradation | p. 255 |
Negative Bias Temperature Instability | p. 256 |
Reaction-Diffusion Model | p. 257 |
Static and Dynamic NBTI | p. 258 |
Design Techniques | p. 260 |
Electrostatic Discharge | p. 261 |
Soft Errors | p. 263 |
Types of Soft Errors | p. 263 |
Soft Error Rate | p. 263 |
SER Mitigation and Correction for Reliability | p. 264 |
Reliability Screening and Testing | p. 264 |
Summary | p. 265 |
References | p. 265 |
Design for Manufacturability: Tools and Methodologies | p. 269 |
Introduction | p. 269 |
DFx in IC Design Flow | p. 270 |
Standard Cell Design | p. 271 |
Library Characterization | p. 272 |
Placement, Routing, and Dummy Fills | p. 274 |
Verification, Mask Synthesis, and Inspection | p. 275 |
Process and Device Simulation | p. 275 |
Electrical DFM | p. 276 |
Statistical Design and Return on Investment | p. 277 |
DFM for Optimization Tools | p. 279 |
DFM-Aware Reliability Analysis | p. 282 |
DFx for Future Technology Nodes | p. 283 |
Concluding Remarks | p. 284 |
References | p. 285 |
Index | p. 287 |
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