9780470072967

Principles of Modern Digital Design

by
  • ISBN13:

    9780470072967

  • ISBN10:

    0470072962

  • Format: Hardcover
  • Copyright: 2007-07-16
  • Publisher: Wiley-Interscience

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Supplemental Materials

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Summary

A major objective of this book is to fill the gap between traditional logic design principles and logic design/optimization techniques used in practice. Over the last two decades several techniques for computer-aided design and optimization of logic circuits have been developed. However, underlying theories of these techniques are inadequately covered or not covered at all in undergraduate text books. This book covers not only the "classical" material found in current text books but also selected materials that modern logic designers need to be familiar with.

Author Biography

Parag K. Lala, PhD, DSc(Eng), is the Cary and Lois Patterson Chair of Electrical Engineering at Texas A&M University-Texarkana. Dr. Lala is the author of five books, including Fault-Tolerant and Fault-Testable Hardware Design and Practical Digital Logic Design and Testing. Dr. Lala was named a Fellow of the IEEE for "contributions to the development of self-checking logic and associated checker design." He is also a Fellow of the Institution of Engineering and Technology, United Kingdom.

Table of Contents

Prefacep. xiii
Number Systems and Binary Codesp. 1
Introductionp. 1
Decimal Numbersp. 1
Binary Numbersp. 2
Basic Binary Arithmeticp. 5
Octal Numbersp. 8
Hexadecimal Numbersp. 11
Signed Numbersp. 13
Diminished Radix Complementp. 14
Radix Complementp. 16
Floating-Point Numbersp. 19
Binary Encodingp. 20
Weighted Codesp. 20
Nonweighted Codesp. 22
Exercisesp. 25
Fundamental Concepts of Digital Logicp. 29
Introductionp. 29
Setsp. 29
Relationsp. 32
Partitionsp. 34
Graphsp. 35
Boolean Algebrap. 37
Boolean Functionsp. 41
Derivation and Classification of Boolean Functionsp. 43
Canonical Forms of Boolean Functionsp. 45
Logic Gatesp. 48
Exercisesp. 53
Combinational Logic Designp. 59
Introductionp. 59
Minimization of Boolean Expressionsp. 60
Karnaugh Mapsp. 63
Don't Care Conditionsp. 68
The Complementary Approachp. 70
Quine-McCluskey Methodp. 73
Simplification of Boolean Function with Don't Caresp. 78
Cubical Representation of Boolean Functionsp. 79
Tautologyp. 82
Complementation Using Shannon's Expansionp. 84
Heuristic Minimization of Logic Circuitsp. 85
Expandp. 85
Reducep. 88
Irredundantp. 90
Espressop. 92
Minimization of Multiple-Output Functionsp. 95
NAND-NAND and NOR-NOR Logicp. 98
NAND-NAND Logicp. 98
NOR-NOR Logicp. 101
Multilevel Logic Designp. 102
Algebraic and Boolean Divisionp. 105
Kernelsp. 106
Minimization of Multilevel Circuits Using Don't Caresp. 109
Satisfiability Don't Caresp. 110
Observability Don't Caresp. 112
Combinational Logic Implementation Using EX-OR and AND Gatesp. 114
Logic Circuit Design Using Multiplexers and Decodersp. 117
Multiplexersp. 117
Demultiplexers and Decodersp. 123
Arithmetic Circuitsp. 125
Half-Addersp. 125
Full Addersp. 126
Carry-Lookahead Addersp. 129
Carry-Select Adderp. 130
Carry-Save Additionp. 130
BCD Addersp. 132
Half-Subtractorsp. 133
Full Subtractorsp. 135
Two's Complement Subtractorsp. 135
BCD Substractorsp. 137
Multiplicationp. 138
Comparatorp. 140
Combinational Circuit Design Using PLDsp. 141
PROMp. 142
PLAp. 144
PALp. 146
Exercisesp. 150
Referencesp. 155
Fundamentals of Synchronous Sequential Circuitsp. 157
Introductionp. 157
Synchronous and Asynchronous Operationp. 158
Latchesp. 159
Flip-Flopsp. 162
D Flip-Flopp. 163
JK Flip-Flopp. 165
T Flip-Flopp. 167
Timing in Synchronous Sequential Circuitsp. 168
State Tables and State Diagramsp. 170
Mealy and Moore Modelsp. 172
Analysis of Synchronous Sequential Circuitsp. 175
Exercisesp. 177
Referencesp. 180
VHDL in Digital Designp. 181
Introductionp. 181
Entity and Architecturep. 182
Entityp. 182
Architecturep. 184
Lexical Elements in VHDLp. 185
Data Typesp. 187
Operatorsp. 189
Concurrent and Sequential Statementsp. 192
Architecture Descriptionp. 194
Structural Descriptionp. 196
Behavioral Descriptionp. 199
RTL Descriptionp. 200
Exercisesp. 202
Combinational Logic Design Using VHDLp. 205
Introductionp. 205
Concurrent Assignment Statementsp. 206
Direct Signal Assignmentp. 206
Conditional Signal Assignmentp. 207
Selected Conditional Signal Assignmentp. 211
Sequential Assignment Statementsp. 214
Processp. 214
If-Then Statementp. 216
Case Statementp. 220
If Versus Case Statementsp. 223
Loopsp. 225
For Loopp. 225
While Loopp. 229
For-Generate statementp. 230
Exercisesp. 233
Synchronous Sequential Circuit Designp. 235
Introductionp. 235
Problem Specificationp. 236
State Minimizationp. 239
Partitioning Approachp. 239
Implication Tablep. 242
Minimization of Incompletely Specified Sequential Circuitsp. 244
Derivation of Flip-Flop Next State Expressionsp. 249
State Assignmentp. 257
State Assignment Based on Decompositionp. 261
Fan-out and Fan-in Oriented State Assignment Techniquesp. 265
State Assignment Based on 1-Hot Codep. 271
State Assignment Using m-out-of-n Codep. 271
Sequential PAL Devicesp. 273
Exercisesp. 286
Referencesp. 290
Counter Designp. 291
Introductionp. 291
Ripple (Asynchronous) Countersp. 291
Asynchronous Up-Down Countersp. 294
Synchronous Countersp. 295
Gray Code Countersp. 300
Shift Register Countersp. 302
Ring Countersp. 307
Johnson Countersp. 310
Exercisesp. 313
Referencesp. 313
Sequential Circuit Design Using VHDLp. 315
Introductionp. 315
D Latchp. 315
Flip-Flops and Registersp. 316
D Flip-Flopp. 316
T and JK Flip-Flopsp. 318
Synchronous and Asynchronous Resetp. 320
Synchronous and Asynchronous Presetp. 322
Registersp. 322
Shift Registersp. 324
Bidirectional Shift Registerp. 326
Universal Shift Registerp. 327
Barrel Shifterp. 327
Linear Feedback Shift Registersp. 329
Countersp. 332
Decade Counterp. 334
Gray Code Counterp. 335
Ring Counterp. 336
Johnson Counterp. 337
State Machinesp. 338
Moore-Type State Machinesp. 338
Mealy-Type State Machinesp. 341
VHDL Codes for State Machines Using Enumerated Typesp. 342
Mealy Machine in VHDLp. 345
User-Defined State Encodingp. 351
1-Hot Encodingp. 355
Case Studiesp. 356
Exercisesp. 368
Referencesp. 371
Asynchronous Sequential Circuitsp. 373
Introductionp. 373
Flow Tablep. 374
Reduction of Primitive How Tablesp. 377
State Assignmentp. 379
Races and Cyclesp. 379
Critical Race-Free State Assignmentp. 381
Excitation and Output Functionsp. 387
Hazardsp. 390
Function Hazardsp. 391
Logic Hazardsp. 393
Essential Hazardsp. 396
Exercisesp. 398
Referencesp. 401
CMOS Logicp. 403
Transmission Gatesp. 405
Clocked CMOS Circuitsp. 407
CMOS Domino Logicp. 408
Indexp. 411
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