Advanced Digital Design with the Verilog HDL

by Ciletti, Michael D.

• ISBN13: 9780130891617
• ISBN10: 0130891614
• Edition: 2nd
• Format: Hardcover
• Copyright: 2011-01-01
• Publisher: Prentice Hall

Summary

This first edtion book covers the key design problems of modeling, architectural tradeoffs, functional verification, timing analysis, test generation, fault simulation, design for testablility, logic synthesis, and post-synthesis verification. The author's focus is on developing, verifying, and synthesizing designs of digital circuits rather than on the Verilog language. Some of the topics covered in this book include Digital Design Methodology, Combinational Logic, Sequential Logic Design, Logic Design with Verilog, and Programmable Logic and Storage Devices. For professional engineers interested in learning Verilog by example, in the context of its use in the design flow of modern integrated circuits.

Table of Contents

1. Introduction to Digital Design Methodology.

Design Methodology - An Introduction. IC Technology Options. Overview.

2. Review of Combinational Logic Design.

Combinational Logic and Boolean Algebra. Theorems for Boolean Algebraic Minimization. Representation of Combinational Logic. Simplification of Boolean Expressions. Glitches and Hazards. Building Blocks for Logic Design.

3. Fundamentals of Sequential Logic Design.

Storage Elements. Flip-Flops. Busses and Three-State Devices. Design of Sequential Machines. State Transition Graphs. Design Example: BCD to Excess-3 Code Converter. Serial Line Code Converter for Data Transmission. State Reduction and Equivalent States.

4. Introduction to Logic Design with Verilog.

Structural Models of Combinational Logic. Logic Simulation, Design Verification, and Testbenches. Propagation Delay. Truth Table Models of Combinational and Sequential Logic with Verilog.

5. Logic Design with Behavioral Models of Combinational and Sequential Logic.

Behavioral Modeling. A Brief Look at Data Types for Behavioral Modeling. Boolean Equation-Based Behavioral Models of Combinational Logic. Propagation Delay and Continuous Assignments. Latches and Level-Sensitive Circuits in Verilog. Cyclic Behavioral Models of Flip-Flops and Latches. Cyclic Behavior and Edge Detection. A Comparison of Styles for Behavioral Modeling. Behavioral Models of Multiplexers, Encoders, and Decoders. Dataflow Models of a Linear Feedback Shift Register. Modeling Digital Machines with Repetitive Algorithms. Machines with Multi-Cycle Operations. Design Documentation with Functions and Tasks: Legacy or Lunacy? Algorithmic State Machine Charts for Behavioral Modeling. ASMD Charts. Behavioral Models of Counters, Shift Registers, and Register Files. Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals. Design Example: Keypad Scanner and Encoder.

6. Synthesis of Combinational and Sequential Logic.

Introduction to Synthesis. Synthesis of Combinational Logic. Synthesis of Sequential Logic with Latches. Synthesis of Three-State Devices and Bus Interfaces. Synthesis of Sequential Logic with Flip-Flops. Synthesis of Explicit State Machines. Registered Logic. State Encoding. Synthesis of Implicit State Machines, Registers, and Counters. Resets. Synthesis of Gated Clocks and Clock Enables. Anticipating the Results of Synthesis. Synthesis of Loops. Design Traps to Avoid. Divide and Conquer: Partitioning a Design.

7. Design and Synthesis of Datapath Controllers.

Partitioned Sequential Machines. Design Example: Binary Counter. Design and Synthesis of a RISC Stored Program Machine. Design Example: UART.

8. Programmable Logic and Storage Devices.

Programmable Logic Devices. Storage Devices. Programmable Logic Array (PLA). Programmable Array Logic (PALTM). Programmability of PLDs. Complex PLDs (CPLDs). Altera MAX 7000 CPLD. XILINX XC9500 CPLDs. Field Programmable Gate Arrays. Altera Flex 8000 FPGAs. Altera Flex 10 FPGAs. Altera Apex FPGAs. Altera Chip Programmability. XILINX XC4000 Series FPGA. XILINX Spartan XL FPGAs. XILINX Spartan II FPGAs. XILINX Virtex FPGAs. Embeddable and Programmable IP Cores for a System on a Chip (SOC). Verilog-Based Design Flows For FPGAs. Synthesis with FPGAs.

9. Architectures and Algorithms for Digital Processors.

Algorithms, Nested Loop Programs, and Data Flow Graphs. Design Example: Halftone Pixel Image Converter. Digital Filters and Signal Processors. Building Blocks for Signal Processors. Pipelined Architectures. Circular Buffers. Dual-Port Fifos and Synchronization Across Clock Domains.

10. Architectures for Arithmetic Processors.

Number Representation. Functional Units for Addition and Subtraction. Functional Units for Multiplication. Multiplication of Signed Binary Numbers. Multiplication of Fractions. Functional Units for Division.

11. Post-Synthesis Design Tasks.

Post-Synthesis Design Validation. Post-Synthesis Timing Verification. Elimination of ASIC Timing Violations. False Paths. Dynamically Sensitized Paths. System Tasks for Timing Verification. Fault Simulation and Testing. Fault Simulation. Fault Simulation with Verifault-XL. JTAG Ports and Design for Testability and BIST.

Appendices.

Verilog Primitives. Verilog Keywords. Verilog Nets. Verilog Data Types, Operators, and Precedence. Backus-Naur (BNF) Formal Syntax Notation. Verilog Language Formal Syntax. System Tasks and Functions. Compiler Directives. Rules for User Defined Primitives. Additional Features of Verilog. Verilog 2001. PLI. Websites. Web-based Tutorials.

Index.

Excerpts

Simplify, Clarify, and VerifyBehavioral modeling with a hardware description language (HDL) is the key to modern design of application-specific integrated circuits (ASICs). Today, most designers use an HDL-based design method to create a high-level, language-based, abstract description of a circuit, synthesize a hardware realization in a selected technology, and verify its functionality and timing.Students preparing to contribute to a productive design team must know how to use an HDL at key stages of the design flow. Thus, there is a need for a course that goes beyond the basic principles and methods learned in a first course in digital design. This book is written for such a course.Many books discussing HDLs are now available, but most are oriented toward robust explanations of language syntax, and are not well-suited for classroom use. Our focus is on design methodology enabled by an HDL.Our goal in this book is to build on a student's background from a first course in logic design by (1) reviewing basic principles of combinational and sequential logic, (2) introducing the use of HDLs in design, (3) emphasizing descriptive styles that will allow the reader to quickly design working circuits suitable for ASICs and/or field-programmable gate array (FPGA) implementation, and (4) providing in-depth design examples using modern design tools. Readers will be encouraged to simplify, clarify, and verify their designs.The widely used Verilog hardware description language (IEEE Standard 1364) serves as a common framework supporting the design activities treated in this book,but our focus is on developing, verifying, and synthesizing designs of digital circuits, not on the Verilog language.Most students taking a second course in digital design will be familiar with at least one programming language and will be able to draw on that background in reading this textbook. We cover only the core and most widely used features of Verilog. In order to emphasizeusingthe language in a synthesis-oriented design environment, we have purposely placed many details, features, and explanations of syntax in the Appendices for reference on an "as-needed" basis.Most entry-level courses in digital design introduce state machines, state-transition graphs, and algorithmic-state machine (ASM) charts. We make heavy use of ASM charts and demonstrate their utility in developing behavioral models of sequential machines. The important problem of designing a finite-state machine to control a complex datapath in a digital machine is treated in-depth with ASMD charts (i.e., ASM charts annotated to display the register operations of the controlled datapath). The design of a reduced instruction-set computer central processing unit (RISC CPU) and other important hardware units are given as examples. Our companion website includes the RISC machine's source code and an assembler that can be used to develop programs for applications. The machine also serves as a starting point for developing a more robust instruction set and architectural variants.The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples. The text has a large set of examples illustrating how to address the key steps in a very large scale integrated (VLSI) circuit design methodology using the Verilog HDL. Examples are complete, and include source code that has been verified with the Silos-III simulator to be correct. Source code for all of the examples will be available (with important test suites) at our website. The Intended AudienceThis book is for students in an advanced course in digital design, and for professional engineers interested in learning Verilog by example, in the context of its use in the design flow of modern integrated circuits.The level of presentation is appropriate for seniors and first-year graduate students in electrical engineering, co