9780201612530

Computer Systems Organization and Architecture

by
  • ISBN13:

    9780201612530

  • ISBN10:

    0201612534

  • Edition: 1st
  • Format: Paperback
  • Copyright: 2000-10-20
  • Publisher: Pearson

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Summary

This book provides up-to-date coverage of fundamental concepts for the design of computers and their subsystems. It presents material with a serious but easy-to-understand writing style that makes it accessible to readers without sacrificing important topics. The book emphasizes a finite state machine approach to CPU design, which provides a strong background for reader understanding. It forms a solid basis for readers to draw upon as they study this material and in later engineering and computer science practice. The book also examines the design of computer systems, including such topics as memory hierarchies, input/output processing, interrupts, and direct memory access, as well as advanced architectural aspects of parallel processing.To make the material accessible to beginners, the author has included two running examples of increasing complexity: the Very Simple CPU, which contains four instruction sets and shows very simple CPU design; and the Relatively Simple CPU which contains 16 instruction sets and adds enough complexity to illustrate more advanced concepts. Each chapter features a real-world machine on which the discussed organization and architecture concepts are implemented.This book is designed to teach computer organization/architecture to engineers and computer scientists.

Author Biography

John D. Carpinelli is an Associate Professor at New Jersey Institute of Technology.

Table of Contents

Preface xvii
Part 1 Digital Logic And Finite State Machines
Digital Logic Fundamentals
3(48)
Boolean Algebra
4(9)
Basic Functions
4(2)
Manipulating Boolean Functions
6(7)
Basic Combinatorial Logic
13(3)
More Complex Combinatorial Components
16(13)
Multiplexers
16(2)
Decoders
18(2)
Encoders
20(1)
Comparators
20(3)
Adders and Subtracters
23(4)
Memory
27(2)
Combinatorial Circuit Designs
29(5)
BCD to 7-segment Decoder
30(1)
Data Sorter
31(1)
Why LED's Are Usually Active Low
32(2)
Basic Sequential Components
34(5)
More Complex Sequential Components
39(4)
Counters
39(2)
Shift Registers
41(2)
Real World Example: Programmable Logic Devices
43(3)
Digital Circuit Implementation
43(3)
Summary
46(5)
Problems
47(4)
Introduction to Finite State Machines
51(52)
State Diagrams and State Tables
52(4)
Finite State Machine and Microprocessors
53(3)
Mealy and Moore Machines
56(2)
Designing State Diagrams
58(8)
Modulo 6 Counter
58(2)
String Checker
60(1)
Toll Booth Controller
61(96)
Different Models for The Same Problem
157
From State Diagram to Implementation
66(17)
Assigning State Values
66(2)
Mealy and Moore Machine Implementations
68(2)
Generating the Next State
70(4)
Generating System Outputs
74(3)
An Alternative Design
77(3)
The Eight-State String Checker
80(3)
Real World Example: Practical Considerations
83(9)
Unused States
83(3)
Asynchronous Designs
86(5)
Machine Conversion
91(1)
Summary
92(11)
Problems
93(10)
Part 2 Computer Organization And Architecture
Instruction Set Architectures
103(38)
Levels of Programming Languages
104(6)
Language Categories
105(1)
Compiling and Assembling Programs
106(3)
Java Applets---A Different Way of Processing Programs
109(1)
Assembly Language Instructions
110(9)
Instruction Types
110(2)
Data Types
112(1)
Addressing Modes
113(2)
Instruction Formats
115(4)
Instruction Set Architecture Design
119(2)
A Relatively Simple Instruction Set Architecture
121(7)
Real World Example: The 8085 Microprocessor Instruction Set Architecture
128(9)
The 8085 Microprocessor Register Set
128(1)
Intel's Early Microprocessors
129(1)
The 8085 Microprocessor Instruction Set
130(4)
A Simple 8085 Program
134(2)
Analyzing the 8085 Instruction Set Architecture
136(1)
Summary
137(4)
Problems
138(3)
Introduction to Computer Organization
141(34)
Basic Computer Organization
142(4)
System Buses
142(1)
Instruction Cycles
143(1)
The Peripheral Component Interconnect Bus
144(2)
CPU Organization
146(2)
Memory Subsystem Organization and Interfacing
148(11)
Types of Memory
149(2)
Internal Chip Organization
151(1)
Memory Subsystem Configuration
152(5)
The Von Neumann and Harvard Architectures
157(1)
Multibyte Data Organization
157(1)
Beyond the Basics
158(1)
I/O Subsystem Organization and Interfacing
159(3)
A Relatively Simple Computer
162(4)
Real World Example: An 8085-based Computer
166(5)
The Sojourner Rover
170(1)
Summary
171(4)
Problems
172(3)
Register Transfer Languages
175(39)
Micro-Operations and Register Transfer Language
176(8)
Using RTL to Specify Digital Systems
184(6)
Specification of Digital Components
185(1)
Specification and Implementation of Simple Systems
186(4)
More Complex Digital Systems and RTL
190(9)
Modulo 6 Counter
190(2)
Toll Booth Controller
192(7)
Real World Example: VHDL-VHSIC Hardware Description Language
199(10)
Hardware Description Languages
200(1)
VHDL Syntax
200(3)
VHDL Design with a High Level of Abstraction
203(4)
VHDL Design with a Low Level of Abstraction
207(2)
Summary
209(5)
Some Advanced Capabilities of VHDL
210(1)
Problems
211(3)
CPU Design
214(53)
Specifying a CPU
214(2)
Design and Implementation of a Very Simple CPU
216(17)
Specifications for a Very Simple CPU
216(1)
Fetching Instructions from Memory
217(1)
Why a CPU Increments PC During the Fetch Cycle
218(1)
Decoding Instructions
219(1)
Executing Instructions
219(2)
Establishing Required Data Paths
221(5)
Design of a Very Simple ALU
226(1)
Designing the Control Unit Using Hardwired Control
227(5)
Design Verification
232(1)
Design and Implementation of a Relatively Simple CPU
233(18)
Specifications for a Relatively Simple CPU
234(2)
Fetching and Decoding Instructions
236(1)
Executing Instructions
237(5)
Establishing Data Paths
242(3)
Design of a Relatively Simple ALU
245(2)
Designing the Control Unit Using Hardwired Control
247(3)
Design Verification
250(1)
Shortcomings of the Simple CPUs
251(5)
More Internal Registers and Cache
251(1)
Storage in Intel Microprocessors
252(1)
Multiple Buses Within the CPU
253(1)
Pipelined Instruction Processing
253(1)
Larger Instruction Sets
253(3)
Subroutines and Interrupts
256(1)
Real World Example: Internal Architecture of the 8085 Microprocessor
256(3)
Summary
259(8)
Problems
259(8)
Microsequencer Control Unit Design
267(41)
Basic Microsequencer Design
268(4)
Microsequencer Operations
268(2)
Microinstruction Formats
270(2)
Design and Implementation of a Very Simple Microsequencer
272(13)
The Basic Layout
272(1)
Generating the Correct Sequence and Designing the Mapping Logic
273(2)
Generating the Micro-Operations Using Horizontal Microcode
275(2)
Generating the Micro-Operations Using Vertical Microcode
277(5)
Nanoinstructions
282(1)
Directly Generating the Control Signals from the Microcode
283(2)
Design and Implementation of a Relatively Simple Microsequencer
285(9)
Modifying the State Diagram
285(1)
Designing the Sequencing Hardware and Microcode
285(6)
Completing the Design Using Horizontal Microcode
291(3)
Reducing the Number of Microinstructions
294(6)
Microsubroutines
294(4)
Microcode Jumps
298(2)
Microprogrammed Control vs. Hardwired Control
300(1)
Complexity of the Instruction Set
300(1)
Ease of Modification
301(1)
Clock Speed
301(1)
Real World Example: A (Mostly) Microcoded CPU: The Pentium Processor
301(3)
How the Pentium Got Its Name
303(1)
Summary
304(4)
Problems
304(4)
Computer Arithmetic
308(68)
Unsigned Notation
309(25)
Addition and Subtraction
310(4)
Multiplication
314(9)
Division
323(11)
Signed Notation
334(6)
Signed-Magnitude Notation
334(5)
Signed-Two's Complement Notation
339(1)
Binary Coded Decimal
340(8)
BCD Numeric Format
341(1)
Addition and Subtraction
341(3)
Multiplication and Division
344(4)
Specialized Arithmetic Hardware
348(10)
Coprocessors
348(1)
Pipelining
349(2)
Lookup Tables
351(1)
The Pentium Floating Point Bug
352(1)
Wallace Trees
353(5)
Floating Point Numbers
358(11)
Numeric Format
358(1)
Numeric Characteristics
359(2)
Addition and Subtraction
361(5)
Multiplication and Division
366(3)
Real World Example: The IEEE 754 Floating Point Standard
369(2)
Formats
369(2)
Denormalized Values
371(1)
Summary
371(5)
Problems
372(4)
Memory Organization
376(46)
Hierarchical Memory Systems
376(2)
Cache Memory
378(18)
Associative Memory
378(2)
Cache Memory with Associative Mapping
380(3)
Cache Memory with Direct Mapping
383(2)
Cache Memory with Set-Associative Mapping
385(2)
Mapping Strategies in Current CPUs
387(1)
Replacing Data in the Cache
388(2)
Writing Data to the Cache
390(1)
Cache Performance
391(5)
Virtual Memory
396(14)
Paging
396(9)
Segmentation
405(3)
Memory Protection
408(2)
Beyond the Basics of Cache and Virtual Memory
410(3)
Beyond the Basics of Cache Memory
410(1)
Cache Hierarchy in the Itanium Microprocessor
411(1)
Beyond the Basics of Virtual Memory
411(2)
Real World Example: Memory Management in a Pentium/Windows Personal Computer
413(1)
Summary
414(8)
Problems
415(7)
Input/Output Organization
422(57)
Asynchronous Data Transfers
422(8)
Source-Initiated Data Transfer
423(2)
Destination-Initiated Data Transfer
425(2)
Handshaking
427(3)
Programmed I/O
430(8)
New Instructions
434(1)
New Control Signals
435(1)
New States and RTL Code
435(1)
Modify the CPU Hardware for the New Instruction
435(2)
Make Sure Other Instructions Still Work
437(1)
Interrupts
438(14)
Transferring Data Between the CPU and I/O Devices
438(2)
Types of Interrupts
440(1)
Processing Interrupts
441(2)
Interrupt Hardware and Priority
443(6)
Implementing Interrupts Inside the CPU
449(3)
Direct Memory Access
452(6)
Incorporating Direct Memory Access (DMA) into a Computer System
452(3)
DMA Transfer Modes
455(1)
Modifying the CPU to Work with DMA
456(2)
I/O Processors
458(4)
The i960 I/O Processor with Built-in DMA
461(1)
Serial Communication
462(5)
Serial Communication Basics
462(4)
Universal Asynchronous Receiver/Transmitters (UARTs)
466(1)
Real World Example: Serial Communication Standards
467(4)
The RS-232-C Standard
468(1)
The RS-422 Serial Standard
469(1)
The Universal Serial Bus Standard
470(1)
Summary
471(8)
Problems
472(7)
Part 3 Advanced Topics
Reduced Instruction Set Computing
479(35)
RISC Rationale
479(4)
Fixed Length Instructions
481(1)
Limited Loading and Storing Instructions Access Memory
481(1)
Fewer Addressing Modes
481(1)
Instruction Pipeline
481(1)
Addressing Modes in the PowerPC 750 RISC CPU
482(1)
Large Number of Registers
482(1)
Hardwired Control Unit
482(1)
Delayed Loads and Branches
482(1)
Speculative Execution of Instructions
483(1)
Optimizing Compiler
483(1)
Separate Instruction and Data Streams
483(1)
RISC Instruction Sets
483(3)
Instruction Pipelines and Register Windows
486(8)
Instruction Pipelines
487(4)
Register Windowing and Renaming
491(3)
Register Windowing and Register Renaming in Real-World CPUs
494(1)
Instruction Pipeline Conflicts
494(10)
Data Conflicts
495(3)
Branch Conflicts
498(6)
RISC vs. CISC
504(2)
Real World Example: The Itanium Microprocessor
506(3)
Summary
509(5)
Problems
509(5)
Introduction to Parallel Processing
514(55)
Parallelism in Uniprocessor Systems
515(4)
Organization of Multiprocessor Systems
519(9)
Flynn's Classification
519(2)
System Topologies
521(3)
MIMD System Architectures
524(2)
The World's Largest Multicomputer?
526(1)
The Blue Gene Computer
527(1)
Communication in Multiprocessor Systems
528(12)
Fixed Connections
528(1)
Reconfigurable Connections
529(5)
Routing on Multistage Interconnection Networks
534(6)
Memory Organization in Multiprocessor Systems
540(7)
Shared Memory
540(2)
Cache Coherence
542(5)
Multiprocessor Operating Systems and Software
547(2)
Parallel Algorithms
549(5)
Parallel Bubble Sort
549(2)
Parallel Matrix Multiplication
551(3)
Alternative Parallel Architectures
554(10)
Dataflow Computing
555(4)
Systolic Arrays
559(3)
Neural Networks
562(2)
Summary
564(5)
Problems
564(5)
Index 569

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