Digital Design

by Mano, M. Morris; Ciletti, Michael D.

• ISBN13: 9780131989245
• ISBN10: 0131989243
• Edition: 4th
• Format: Hardcover w/Disk
• Copyright: 2007-01-01
• Publisher: Prentice Hall

Summary

For sophomore courses on digital design in an Electrical Engineering, Computer Engineering, or Computer Science department. Digital Design, fourth edition is a modern update of the classic authoritative text on digital design. This book teaches the basic concepts of digital design in a clear, accessible manner. The book presents the basic tools for the design of digital circuits and provides procedures suitable for a variety of digital applications.

Table of Contents

Preface	p. ix
Digital Systems and Binary Numbers	p. 1
Digital Systems	p. 1
Binary Numbers	p. 3
Number-Base Conversions	p. 5
Octal and Hexadecimal Numbers	p. 8
Complements	p. 9
Signed Binary Numbers	p. 14
Binary Codes	p. 17
Binary Storage and Registers	p. 25
Binary Logic	p. 28
Boolean Algebra and Logic Gates	p. 36
Introduction	p. 36
Basic Definitions	p. 36
Axiomatic Definition of Boolean Algebra	p. 38
Basic Theorems and Properties of Boolean Algebra	p. 41
Boolean Functions	p. 44
Canonical and Standard Forms	p. 48
Other Logic Operations	p. 55
Digital Logic Gates	p. 57
Integrated Circuits	p. 63
Gate-Level Minimization	p. 70
Introduction	p. 70
The Map Method	p. 70
Four-Variable Map	p. 76
Five-Variable Map	p. 81
Product-of-Sums Simplification	p. 83
Don't-Care Conditions	p. 86
NAND and NOR Implementation	p. 89
Other Two-Level Implementations	p. 96
Exclusive-OR Function	p. 101
Hardware Description Language	p. 106
Combinational Logic	p. 122
Introduction	p. 122
Combinational Circuits	p. 122
Analysis Procedure	p. 123
Design Procedure	p. 126
Binary Adder-Subtractor	p. 130
Decimal Adder	p. 139
Binary Multiplier	p. 142
Magnitude Comparator	p. 144
Decoders	p. 146
Encoders	p. 150
Multiplexers	p. 152
HDL Models of Combinational Circuits	p. 159
Synchronous Sequential Logic	p. 182
Introduction	p. 182
Sequential Circuits	p. 182
Storage Elements: Latches	p. 184
Storage Elements: Flip-Flops	p. 188
Analysis of Clocked Sequential Circuits	p. 195
Synthesizable HDL Models of Sequential Circuits	p. 207
State Reduction and Assignment	p. 227
Design Procedure	p. 225
Registers and Counters	p. 242
Registers	p. 242
Shift Registers	p. 245
Ripple Counters	p. 253
Synchronous Counters	p. 258
Other Counters	p. 265
HDL for Registers and Counters	p. 269
Memory and Programmable Logic	p. 284
Introduction	p. 284
Random-Access Memory	p. 285
Memory Decoding	p. 291
Error Detection and Correction	p. 296
Read-Only Memory	p. 299
Programmable Logic Array	p. 305
Programmable Array Logic	p. 309
Sequential Programmable Devices	p. 311
Design at the Register Transfer Level	p. 334
Introduction	p. 334
Register Transfer Level (RTL) Notation	p. 334
Register Transfer Level in HDL	p. 336
Algorithmic State Machines (ASMs)	p. 345
Design Example	p. 352
HDL Description of Design Example	p. 367
Sequential Binary Multiplier	p. 371
Control Logic	p. 376
HDL Description of Binary Multiplier	p. 382
Design with Multiplexers	p. 390
Race-Free Design	p. 407
Latch-Free Design	p. 403
Other Language Features	p. 404
Asynchronous Sequential Logic	p. 415
Introduction	p. 415
Analysis Procedure	p. 477
Circuits with Latches	p. 425
Design Procedure	p. 433
Reduction of State and Flow Tables	p. 439
Race-Free State Assignment	p. 446
Hazards	p. 452
Design Example	p. 457
Digital Integrated Circuits	p. 471
Introduction	p. 471
Special Characteristics	p. 473
Bipolar-Transistor Characteristics	p. 477
RTL and DTL Circuits	p. 481
Transistor-Transistor Logic	p. 484
Emitter-Coupled Logic	p. 493
Metal-Oxide Semiconductor	p. 495
Complementary MOS	p. 498
CMOS Transmission Gate Circuits	p. 501
Switch-Level Modeling with HDL	p. 505
Laboratory Experiments with Standard ICs and FPGAs 57	p. 511
Introduction to Experiments	p. 511
Experiment 1: Binary and Decimal Numbers	p. 516
Experiment 2: Digital Logic Gates	p. 579
Experiment 3: Simplification of Boolean Functions	p. 520
Experiment 4: Combinational Circuits	p. 522
Experiment 5: Code Converters	p. 524
Experiment 6: Design with Multiplexers	p. 526
Experiment 7: Adders and Subtractors	p. 527
Experiment 8: Flip-Flops	p. 550
Experiment 9: Sequential Circuits	p. 532
Experiment 10: Counters	p. 534
Experiment 11: Shift Registers	p. 535
Experiment 12: Serial Addition	p. 538
Experiment 13: Memory Unit	p. 539
Experiment 14: Lamp Handball	p. 547
Experiment 15: Clock-Pulse Generator	p. 545
Experiment 16: Parallel Adder and Accumulator	p. 547
Experiment 17: Binary Multiplier	p. 549
Experiment 18: Asynchronous Sequential Circuits	p. 553
Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs	p. 553
Standard Graphic Symbols	p. 589
Rectangular-Shape Symbols	p. 559
Qualifying Symbols	p. 562
Dependency Notation	p. 564
Symbols for Combinational Elements	p. 566
Symbols for Flip-Flops	p. 550
Symbols for Registers	p. 570
Symbols for Counters	p. 573
Symbol for RAM	p. 575
Answers to Selected Problems	p. 577
Index	p. 597
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