Digital Design Principles and Practices

by Wakerly, John F.

• ISBN13: 9780131863897
• ISBN10: 0131863894
• Edition: 4th
• Format: Hardcover
• Copyright: 2005-07-21
• Publisher: Pearson

Summary

Appropriate for a first or second course in digital logic design. Blends academic precision and practical experience in an authoritative introduction to basic principles of digital design and practical requirements. With over 30 years of experience in both industrial and university settings, the author covers the most widespread logic design practices while building a solid foundation of theoretical and engineering principles for students to use as they go forward in this fast moving field.

Table of Contents

Preface	xv
Introduction	1	(24)
About Digital Design	1	(2)
Analog versus Digital	3	(3)
Digital Devices	6	(1)
Electronic Aspects of Digital Design	7	(1)
Software Aspects of Digital Design	8	(3)
Integrated Circuits	11	(3)
Programmable Logic Devices	14	(2)
Application-Specific ICs	16	(1)
Printed-Circuit Boards	17	(1)
Digital-Design Levels	18	(4)
The Name of the Game	22	(1)
Going Forward	23	(2)
Drill Problems	23	(2)
Number Systems and Codes	25	(54)
Positional Number Systems	26	(1)
Octal and Hexadecimal Numbers	27	(2)
General Positional-Number-System Conversions	29	(3)
Addition and Subtraction of Nondecimal Numbers	32	(2)
Representation of Negative Numbers	34	(5)
Signed-Magnitude Representation
Complement Number Systems
Radix-Complement Representation
Two's-Complement Representation
Diminished Radix-Complement Representation
Ones'-Complement Representation
Excess Representations
Two's-Complement Addition and Subtraction	39	(5)
Addition Rules
A Graphical View
Overflow
Subtraction Rules
Two's-Complement and Unsigned Binary Numbers
Ones'-Complement Addition and Subtraction	44	(1)
Binary Multiplication	45	(2)
Binary Division	47	(1)
Binary Codes for Decimal Numbers	48	(3)
Gray Code	51	(2)
Character Codes	53	(1)
Codes for Actions, Conditions, and States	53	(4)
n-Cubes and Distance	57	(1)
Codes for Detecting and Correcting Errors	58	(11)
Error-Detecting Codes
Error-Correcting and Multiple-Error-Detecting Codes
Hamming Codes
CRC Codes
Two-Dimensional Codes
Checksum Codes
m-out-of-n Codes
Codes for Serial Data Transmission and Storage	69	(10)
Parallel and Serial Data
Serial Line Codes
References	73	(1)
Drill Problems	74	(2)
Exercises	76	(3)
Digital Circuits	79	(104)
Logic Signals and Gates	80	(4)
Logic Families	84	(2)
CMOS Logic	86	(10)
CMOS Logic Levels
MOS Transistors
Basic CMOS Inverter Circuit
COMOS NAND and NOR Gates
Fan-In
Noninverting Gates
CMOS And-Or-Invert and Or-and-Invert Gates
Electrical Behavior of CMOS Circuits	96	(5)
Overview
Data Sheets and Specifications
CMOS Static Electrical Behavior	101	(13)
Logic Levels and Noise Margins
Circuit Behavior with Resistive Loads
Circuit Behavior with Nonideal Inputs
Fanout
Effects of Loading
Unused Inputs
How to Destroy a CMOS Device
CMOS Dynamic Electrical Behavior	114	(15)
Transition Time
Propagation Delay
Power Consumption
Current Spikes and Decoupling Capacitors
Inductive Effects
Simultaneous Switching and Ground Bounce
Other CMOS Input and Output Structures	129	(12)
Transmission Gates
Schmitt-Trigger Inputs
Three-State Outputs
Open-Drain Outputs
Driving LEDs
Multisource Buses
Wired Logic
Pull-Up Resistors
CMOS Logic Families	141	(10)
HC and HCT
AHC and AHCT
HC, HCT, AHC, and AHCT Electrical Characteristics
AC and ACT
FCT and FCT-T
FCT-T Electrical Characteristics
Low-Voltage CMOS Logic and Interfacing	151	(4)
VLVTTL and LVCMOS Logic
5-V Tolerant Inputs
5-V Tolerant Outputs
TTL/LVTTL Interfacing Summary
Logic Levels Less Than 3.3 V
Bipolar Logic	155	(28)
Diode Logic
Bipolar Junction Transistors
Transistor-Transistor Logic
TTL Logic Levels and Noise Margins
TTL Fanout
TTL Families
A TTL Data Sheet
CMOS/TTL Interfacing
Emitter-Coupled Logic
References	174	(1)
Drill Problems	175	(4)
Exercises	179	(4)
Combinational Logic Design Principles	183	(54)
Switching Algebra	184	(15)
Axioms
Single-Variable Theorems
Two-and Three-Variable Theorems
n-Variable Theorems
Duality
Standard Representations of Logic Functions
Combinational-Circuit Analysis	199	(6)
Combinational-Circuit Synthesis	205	(19)
Circuit Descriptions and Designs
Circuit Manipulations
Combinational-Circuit Minimization
Karnaugh Maps
Minimizing Sums of Products
Other Minimization Topics
Programmed Minimization Methods
Timing Hazards	224	(13)
Static Hazards
Finding Static Hazards Using Maps
Dynamic Hazards
Designing Hazard-Free Circuits
References	229	(1)
Drill Problems	230	(2)
Exercises	232	(5)
Hardware Description Languages	237	(104)
HDL-Based Digital Design	238	(5)
Why HDLs?
HDL Tool Suites
HDL-Based Design Flow
The ABEL Hardware Description Language	243	(13)
ABEL Program Structure
ABEL Compiler Operation
WHEN Statements and Equation Blocks
Truth Tables
Ranges, Sets, and Relations
Test Vectors
Additional ABEL Features
The VHDL Hardware Description Language	256	(34)
Program Structure
Types, Constants, and Arrays
Functions and Procedures
Libraries and Packages
Structural Design Elements
Dataflow Design Elements
Behavioral Design Elements
The Time Dimension
Simulation
Test Benches
VHDL Features for Sequential Logic Design
Synthesis
The Verilog Hardware Description Language	290	(51)
Program Structure
Logic System, Nets, Variables, and Constants
Vectors and Operators
Arrays
Logical Operators and Expressions
Compiler Directives
Structural Design Elements
Dataflow Design Elements
Behavioral Design Elements (Procedural Code)
Functions and Tasks
The Time Dimension
Simulation
Test Benches
Verilog Features for Sequential Logic Design
Synthesis
References	335	(2)
Drill Problems	337	(1)
Exercises	338	(3)
Combinational Logic Design Practices	341	(180)
Documentation Standards	342	(20)
Block Diagrams
Gate Symbols
Signal Names and Active Levels
Active Levels for Pins
Bubble-to-Bubble Logic Design
Signal Naming in HDL Programs
Drawing Layout
Buses
Additional Schematic Information
Circuit Timing	362	(8)
Timing Diagrams
Propagation Delay
Timing Specifications
Timing Analysis
Timing Analysis Tools
Combinational PLDs	370	(14)
Programmable Logic Arrays
Programmable Array Logic Devices
Generic Array Logic Devices
Complex Programmable Logic Devices (CPLDs)
CMOS PLD Circuits
Device Programming and Testing
Decoders	384	(24)
Binary Decoders
Logic Symbols for Larger-Scale Elements
The 74x138 3-to-8 Decoder
Cascading Binary Decoders
Decoders in ABEL and PLDs
Decoders in VHDL
Decoders in Verilog
Seven-Segment Decoders
Encoders	408	(10)
Priority Encoders
The 74x148 Priority Encoder
Encoders in ABEL and PLDs
Encoders in VHDL
Encoders in Verilog
Three-State Devices	418	(14)
Three-State Buffers
Standard MSI Three-State Buffers
Three-State Outputs in ABEL and PLDs
Three-State Outputs in VHDL
Three-State Outputs in Verilog
Multiplexers	432	(15)
Standard MSI Multiplexers
Expanding Multiplexers
Multiplexers, Demultiplexers, and Buses
Multiplexers in ABEL and PLDs
Multiplexers in VHDL
Multiplexers in Verilog
Exclusive-OR Gates and Parity Circuits	447	(11)
Exclusive-OR and Exclusive-NOR Gates
Parity Circuits
The 74x280 9-Bit Parity Generator
Parity-Checking Applications
Exclusive-OR Gates and Parity Circuits in ABEL and PLDs
Exclusive-OR Gates and Parity Circuits in VHDL
Exclusive-OR Gates and Parity Circuits in Verilog
Comparators	458	(16)
Comparator Structure
Iterative Circuits
An Iterative Comparator Circuit
Standard MSI Magnitude Comparators
Comparators in HDLs
Comparators in ABEL and PLDs
Comparators in VHDL
Comparators in Verilog
Adders, Subtractors, and ALUs	474	(20)
Half Adders and Full Adders
Ripple Adders
Subtractors
Carry-Lookahead Adders
MSI Adders
MSI Arithmetic and Logic Units
Group-Carry Lookahead
Adders in ABEL and PLDs
Adders in VHDL
Adders in Verilog
Combinational Multipliers	494	(27)
Combinational Multiplier Structures
Multiplication in ABEL and PLDs
Multiplication in VHDL
Multiplication in Verilog
References	508	(1)
Drill Problems	509	(2)
Exercises	511	(10)
Sequential Logic Design Principles	521	(158)
Bistable Elements	523	(3)
Digital Analysis
Analog Analysis
Metastable Behavior
Latches and Flip-Flops	526	(16)
S-R Latch
S-R Latch
S-R Latch with Enable
D Latch
Edge-Triggered D Flip-Flop
Edge-Triggered D Flip-Flop with Enable
Scan Flip-Flop
Master/Slave S-R Flip-Flop
Master/Slave J-K Flip-Flop
Edge-Triggered J-K Flip-Flop
T Flip-Flop
Clocked Synchronous State-Machine Analysis	542	(11)
State-Machine Structure
Output Logic
Characteristic Equations
Analysis of State Machines with D Flip-Flops
Clocked Synchronous State-Machine Design	553	(17)
State-Table Design Example
State Minimization
State Assignment
Synthesis Using D Flip-Flops
Synthesis Using J-K Flip-Flops
More Design Examples Using D Flip-Flops
Designing State Machines Using State Diagrams	570	(7)
State-Machine Synthesis Using Transition Lists	577	(3)
Transition Equations
Excitation Equations
Variations on the Scheme
Realizing the State Machine
Another State-Machine Design Example	580	(7)
The Guessing Game
Unused States
Output-Coded State Assignment
``Don't-Care'' State Codings
Decomposing State Machines	587	(3)
Feedback Sequential-Circuit Analysis	590	(11)
Basic Analysis
Analyzing Circuits with Multiple Feedback Loops
Races
State Tables and Flow Tables
CMOS D Flip-Flop Analysis
Feedback Sequential-Circuit Design	601	(11)
Latches
Designing Fundamental-Mode Flow Table
Flow-Table Minimization
Race-Free State Assignment
Excitation Equations
Essential Hazards
Summary
ABEL Sequential-Circuit Design Features	612	(13)
Registered Outputs
State Diagrams
External State Memory
Specifying Moore Outputs
Specifying Mealy and Pipelined Outputs with WITH
Test Vectors
Sequential-Circuit Design with VHDL	625	(21)
Clocked Circuits
State-Machine Design with VHDL
A VHDL State-Machine Example
State Assignment in VHDL
Pipelined Outputs in VHDL
Direct VHDL Coding Without a State Table
More VHDL State-Machine Examples
Specifying Flip-Flops in VHDL
VHDL State-Machine Test Benches
Feedback Sequential Circuits
Sequential-Circuit Design with Verilog	646	(33)
Clocked Circuits
State-Machine Design with Verilog
A Verilog State-Machine Example
Pipelined Outputs in Verilog
Direct Verilog Coding Without a State Table
More Verilog State-Machine Examples
Specifying Flip-Flops in Verilog
Verilog State-Machine Test Benches
Feedback Sequential Circuits
References	663	(1)
Drill Problems	664	(5)
Exercises	669	(10)
Sequential Logic Design Practices	679	(120)
Sequential-Circuit Documentation Standards	680	(6)
General Requirements
Logic Symbols
State-Machine Descriptions
Timing Diagrams and Specifications
Latches and Flip-Flops	686	(17)
SSI Latches and Flip-Flops
Switch Debouncing
The Simplest Switch Debouncer
Bus Holder Circuit
Multibit Registers and Latches
Registers and Latches in ABEL and PLDs
Registers and Latches in VHDL
Registers and Latches in Verilog
Sequential PLDs	703	(7)
Sequential GAL Devices
PLD Timing Specifications
Counters	710	(17)
Ripple Counters
Synchronous Counters
MSI Counters and Applications
Decoding Binary-Counter States
Counters in ABEL and PLDs
Counters in VHDL
Counters in Verilog
Shift Registers	727	(29)
Shift-Register Structure
MSI Shift Registers
Shift-Register Counters
Ring Counters
Johnson Counters
Linear Feedback Shift-Register Counters
Shift Registers in ABEL and PLDs
Shift Registers in VHDL
Shift Registers in Verilog	752	(4)
Iterative versus Sequential Circuits	756	(2)
Synchronous Design Methodology	758	(4)
Synchronous System Structure
Impediments to Synchronous Design	762	(7)
Clock Skew
Gating the Clock
Asynchronous Inputs
Synchronizer Failure and Metastability	769	(30)
Synchronizer Failure
Metastability Resolution Time
Reliable Synchronizer Design
Analysis of Metastable Timing
Better Synchronizers
Other Synchronizer Designs
Synchronizing High-Speed Data Transfers
References	788	(2)
Drill Problems	790	(2)
Exercises	792	(7)
Memory, CPLDS, and FPGAS	799	(64)
Read-Only Memory	800	(21)
Using ROMs for ``Random'' Combinational Logic Functions
Internal ROM Structure
Two-Dimensional Decoding
Commercial ROM Types
ROM Control Inputs and Timing
ROM Applications
Read/Write Memory	821	(1)
Static RAM	822	(11)
Static-RAM Inputs and Outputs
Static-RAM Internal Structure
Static-RAM Timing
Standard Static RAMs
Synchronous SRAM
Dynamic RAM	833	(7)
Dynamic-RAM Structure
SDRAM Timing
DDR SDRAMs
Complex Programmable Logic Devices	840	(10)
Xilinx XC9500 CPLD Family
Function-Block Architecture
Input/Output-Block Architecture
Switch Matrix
Field-Programmable Gate Arrays	850	(13)
Xilinx XC4000 FPGA Family
Configurable Logic Block
Input/Output Block
Programmable Interconnect
References	859	(1)
Drill Problems	859	(1)
Exercises	860	(3)
Index	863