Digital Logic Design and Computer Organization With Computer Architecture for Security

by Faroughi, Nikrouz

• ISBN13: 9780071836906
• ISBN10: 007183690X
• Edition: 1st
• Format: Hardcover
• Copyright: 2014-09-11
• Publisher: McGraw-Hill Education

Summary

A COMPREHENSIVE GUIDE TO THE DESIGN & ORGANIZATION OF MODERN COMPUTING SYSTEMS

Digital Logic Design and Computer Organization with Computer Architecture for Security provides practicing engineers and students with a clear understanding of computer hardware technologies. The fundamentals of digital logic design as well as the use of the Verilog hardware description language are discussed. The book covers computer organization and architecture, modern design concepts, and computer security through hardware.

Techniques for designing both small and large combinational and sequential circuits are thoroughly explained. This detailed reference addresses memory technologies, CPU design and techniques to increase performance, microcomputer architecture, including "plug and play" device interface, and memory hierarchy. A chapter on security engineering methodology as it applies to computer architecture concludes the book. Sample problems, design examples, and detailed diagrams are provided throughout this practical resource.

COVERAGE INCLUDES:

• Combinational circuits: small designs
• Combinational circuits: large designs
• Sequential circuits: core modules
• Sequential circuits: small designs
• Sequential circuits: large designs
• Memory
• Instruction set architecture
• Computer architecture: interconnection
• Memory system
• Computer architecture: security

Table of Contents

1 Introduction
1.1 Introduction
1.1.1 Data Representation
1.1.2 Data Path
1.1.3 Computer Systems
1.1.4 Embedded Systems
1.2 Logic Design
1.2.1 Circuit Minimization
1.2.2 Implementation
1.2.3 Types of Circuits
1.2.4 Computer-Aided Design Tools
1.3 Computer Organization
1.4 Computer Architecture
1.4.1 Pipelining
1.4.2 Parallelism
1.5 Computer Security
References
Exercises
2 Combinational Circuits: Small Designs
2.1 Introduction
2.1.1 Signal Naming Standards
2.2 Logic Expressions
2.2.1 Sum of Product Expression
2.2.2 Product of Sum Expression
2.3 Canonical Expression
2.3.1 Min-Terms
2.3.2 Max-Terms
2.4 Logic Minimization
2.4.1 Karnaugh Map
2.4.2 K-Map Minimization
2.5 Logic Minimization Algorithm
2.5.1 Minimization Software
2.6 Circuit Timing Diagram
2.6.1 Signal Propagation Delay
2.6.2 Fan-In and Fan-Out
2.7 Other Gates
2.7.1 Buffer
2.7.2 Open Collector Buffer
2.7.3 Tri-State Buffer
2.8 Design Examples
2.8.1 Full Adder
2.8.2 Multiplexer
2.8.3 Decoder
2.8.4 Encoder
2.9 Implementation
2.9.1 Programmable Logic Devices
2.9.2 Design Flow
2.10 Hardware Description Languages
2.10.1 Structural Model
2.10.2 Propagation Delay Simulation
2.10.3 Behavioral Modeling
2.10.4 Synthesis and Simulation
References
Exercises
3 Combinational Circuits: Large Designs
3.1 Introduction
3.1.1 Top-Down Design Methodology
3.2 Arithmetic Functions
3.3 Adder
3.3.1 Carry Propagate Adder
3.3.2 Carry Look-Ahead Adder
3.4 Subtractor
3.5 2’s Complement Adder/Subtractor
3.6 Arithmetic Logic Unit
3.6.1 Design Partitioning: Bit-Parallel
3.6.2 Design Partitioning: Bit-Serial
3.7 Design Examples
3.7.1 Multiplier
3.7.2 Divider
3.8 Real Number Arithmetic
3.8.1 Floating-Point Standards
3.8.2 Floating-Point Data Space
3.8.3 Floating-Point Arithmetic
3.8.4 Floating-Point Unit
References
Exercises
4 Sequential Circuits: Core Modules
4.1 Introduction
4.2 SR Latch
4.2.1 Clocked SR Latch
4.3 D-Latch
4.4 Disadvantage of Latches
4.5 D Flip-Flop
4.5.1 Alternative Circuit
4.5.2 Operating Conventions
4.5.3 Setup and Hold Times
4.6 Clock Frequency Estimation without Clock Skew
4.7 Flip-Flop with Enable
4.8 Other Flip-Flops
4.9 Hardware Description Language Models
References
Exercises
5 Sequential Circuits: Small Designs
5.1 Introduction
5.2 Introduction to FSM: Register Design
5.2.1 Register Model
5.2.2 Multifunction Registers
5.3 Finite State Machine Design
5.3.1 Binary Encoded States
5.3.2 One-Hot Encoded States
5.4 Counters
5.5 Fault-Tolerant Finite State Machine
5.5.1 Hamming Coding Scheme
5.6 Sequential Circuit Timing
5.6.1 Clock Frequency Estimation with Clock Skew
5.6.2 Asynchronous Interface
5.7 Hardware Description Language Models
5.7.1 Synthesis and Simulation
References
Exercises
6 Sequential Circuits: Large Designs
6.1 Introduction
6.1.1 Register Transfer Notation
6.2 Data Path Design
6.2.1 Single-Cycle
6.2.2 Multicycle
6.2.3 Pipelined
6.3 Control Unit Design Techniques
6.3.1 Hardwired Control: FSD
6.3.2 Microprogrammed Control
6.3.3 Hardwire Control: Pipeline
6.4 Energy and Power Consumption
6.5 Design Examples
6.5.1 Unsigned Sequential Multiplier
6.5.2 Signed Sequential Multiplier
6.5.3 Computer Graphics: Rotation
References
Exercises
7 Memory
7.1 Introduction
7.2 Memory Technologies
7.2.1 Read-Only Memories
7.2.2 Random Access Memories
7.2.3 Applications
7.3 Memory Cell Array
7.3.1 Word Access
7.3.2 Burst Access
7.4 Memory Organization
7.4.1 Modern DRAMs
7.4.2 SRAM Cell Model
7.4.3 Internal Organization: SRAM Chip
7.4.4 Memory Unit Design
7.5 Memory Timing
7.5.1 SRAM
7.5.2 DRAM
7.5.3 SDRAM
7.5.4 DDR SDRAM
7.6 Memory Architecture
7.6.1 High-Order Interleaving
7.6.2 Low-Order Interleaving
7.6.3 Multichannel
7.7 Design Example: Multiprocessor Memory Architecture
7.7.1 UMA versus NUMA
7.7.2 A NUMA Application
7.8 HDL Models
References
Exercises
8 Instruction Set Architecture
8.1 Introduction
8.1.1 Type of Instructions
8.1.2 Program Translation
8.1.3 Instruction Cycle
8.2 Types of Instruction Set Architecture
8.2.1 Addressing Modes
8.2.2 Instruction Format
8.2.3 Stack-ISA
8.2.4 Accumulator-ISA
8.2.5 CISC-ISA
8.2.6 RISC-ISA
8.3 Design Example
8.3.1 Acc-ISA Instruction Set Design
8.3.2 Acc-ISA Processor: Single-Cycle
8.3.3 Acc-ISA Processor: Pipelined
8.3.4 RISC-ISA Processor
8.4 Advanced Processor Architectures
8.4.1 Deep Pipelining
8.4.2 Branch Prediction
8.4.3 Instruction-Level Parallelism
8.4.4 Multithreading
References
Exercises
9 Computer Architecture: Interconnection
9.1 Introduction
9.1.2 Interconnection Architectures
9.2 Memory Controller
9.2.1 Simple Memory Controller
9.2.2 Modern Memory Controller
9.3 I/O Peripheral Devices
9.4 Controlling and Interfacing I/O Devices
9.4.1 I/O Ports
9.5 Data Transfer Mechanisms
9.5.1 Interrupt-Driven Transfer
9.5.2 Programmed Transfer
9.5.3 DMA Transfer
9.6 Interrupts
9.6.1 Handling Interruptions
9.6.2 Interrupt Structures
9.7 Design Example: Interrupt Handling CPU
9.8 USB Host Controller Interface
9.8.1 Standards
9.8.2 Transactions
9.8.3 Transfers
9.8.4 Descriptors
9.8.5 Frames
9.8.6 Transaction Organization
9.8.7 Transaction Execution
References
Exercises
10 Memory System
10.1 Introduction
10.1.1 Memory Hierarchy
10.2 Cache Mapping
10.2.1 Direct Mapping
10.2.2 Types of Cache Misses
10.2.3 Set-Associative Mapping
10.3 Cache Coherency
10.3.1 Invalidation versus Update Protocols
10.3.2 Snoop Cache Coherence Protocol
10.3.3 Write-Through Protocol
10.3.4 Write-Back Protocols
10.4 Virtual Memory
10.4.1 Virtual Address Translation
10.4.2 Translation Lookaside Buffer
10.4.3 Processor Organization
References
Exercises
11 Computer Architecture: Security
11.1 Introduction
11.1.1 Security Engineering Methodology
11.1.2 Threat Classes
11.1.3 Access Control and Types
11.1.4 Security Policy Models
11.1.5 Attack Classes
11.2 Hardware Backdoor Attacks
11.2.1 Data and Control Attacks
11.2.2 Timer Attack
11.2.3 Security Policy Mechanisms
11.3 Software/Physical Attacks
11.3.1 Spoofing
11.3.2 Splicing
11.3.3 Replay
11.3.4 Man-in-the-Middle
11.4 Trusted Computing Base
11.5 Cryptography
11.5.1 Symmetric-Key Ciphers
11.5.2 Modes of Operation
11.5.3 Asymmetric-Key Ciphers
11.6 Hashing
11.7 Cryptography Hash
11.7.1 Message Authentication Code
11.7.2 Hash MAC
11.8 Storing Cryptography Keys through Hardware
11.8.1 Keychain Organization
11.8.2 Storage and Access
11.8.3 Application Example: Keychain as Access Control
11.9 Hash Tree
11.9.1 Application Example: Keychain Authentication
11.9.2 Application Example: Memory Authentication
11.10 Secure Coprocessor Architecture
11.10.1 Trusted Platform Module
11.11 Secure Processor Architecture
11.11.1 Program Code Integrity
11.11.2 Operational Security Mechanisms
11.11.3 Program Code Confidentiality
11.11.4 Program Code Integrity and Confidentiality
11.11.5 Program Data Integrity
11.11.6 Program Data Confidentiality
11.11.7 Program Data Integrity and Confidentiality
11.11.8 Program Code and Data Integrity and Confidentiality
11.11.9 Handling Interruption
11.12 Design Example: Secure Processor
11.12.1 SP Specification
11.12.2 Processor Architecture
11.12.3 Encryption Decryption Hashing Engine
11.12.4 Hash Tree Engine
11.13 Further Reading
References
Exercises
Bibliography
Index