High Performance Embedded Architectures and Compilers: Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings

by De Bosschere, Koen; Kaeli, David; Stenstrom, Per; Whalley, David; Ungerer, Theo

• ISBN13: 9783540693376
• ISBN10: 3540693378
• Format: Paperback
• Copyright: 2007-03-06
• Publisher: Springer Verlag

Summary

This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in Januar 2007. The 19 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on secure and low-power embedded memory systems, architecture/compiler optimizations for efficient embedded processing, adaptive microarchitectures, architecture evaluation techniques, generation of efficient embedded applications, as well as optimizations and architectural tradeoffs for embedded systems.

Table of Contents

Abstract of keynote : insight, not (random) numbers : an embedded perspective	p. 3
Compiler-assisted memory encryption for embedded processors	p. 7
Leveraging high performance data cache techniques to save power in embedded systems	p. 23
Applying decay to reduce dynamic power in set-associative caches	p. 38
Virtual registers : reducing register pressure without enlarging the register file	p. 57
Bounds checking with taint-based analysis	p. 71
Reducing exit stub memory consumption in code caches	p. 87
Reducing branch misprediction penalties via adaptive pipeline scaling	p. 105
Fetch gating control through speculative instruction window weighting	p. 120
Dynamic capacity-speed tradeoffs in SMT processor caches	p. 136
Branch history matching : branch predictor warmup for sampled simulation	p. 153
Sunflower : full-system, embedded microarchitecture evaluation	p. 168
Efficient program power behavior characterization	p. 183
Performance/energy optimization of DSP transforms on the XScale processor	p. 201
Arx : a toolset for the efficient simulation and direct synthesis of high-performance signal processing algorithms	p. 215
A throughput-driven task creation and mapping for network processors	p. 227
MiDataSets : creating the conditions for a more realistic evaluation of iterative optimization	p. 245
Evaluation of offset assignment heuristics	p. 261
Customizing the datapath and ISA of soft VLIW processors	p. 276
Instruction set extension generation with considering physical constraints	p. 291
Table of Contents provided by Blackwell. All Rights Reserved.