High Speed Cmos Design Styles

by Bernstein, Kerry; Carrig, Keith M.; Durham, Christopher M.; Hansen, Patrick R.; Hogenmiller, David; Nowak, Edward J.

• ISBN13: 9780792382201
• ISBN10: 079238220X
• Format: Hardcover
• Copyright: 1998-07-01
• Publisher: Kluwer Academic Pub

Summary

High Speed CMOS Design Styles is written for the graduate-level student or practicing engineer who is primarily interested in circuit design. It is intended to provide practical reference, or `horse-sense', to mechanisms typically described with a more academic slant. This book is organized so that it can be used as a textbook or as a reference book. High Speed CMOS Design Styles provides a survey of design styles in use in industry, specifically in the high speed microprocessor design community. Logic circuit structures, I/O and interface, clocking, and timing schemes are reviewed and described. Characteristics, sensitivities and idiosyncrasies of each are highlighted. High Speed CMOS Design Styles also pulls together and explains contributors to performance variability that are associated with process, applications conditions and design. Rules of thumb and practical references are offered. Each of the general circuit families is then analyzed for its sensitivity and response to this variability. High Speed CMOS Design Styles is an excellent source of ideas and a compilation of observations that highlight how different approaches trade off critical parameters in design and process space.

Table of Contents

Preface	v
CHAPTER 1 Process Variability	1	(50)
1.1 Introduction	1	(5)
1.1.1 Inter-Die Variations: Across-Lot and Across-Wafer Variation	2	(3)
1.1.2 Intra-Die Variation	5	(1)
1.1.3 Fail Causes	5	(1)
1.2 Front-End-Of-Line Variability Considerations	6	(19)
1.2.1 Short Channel Effects and ACLV	6	(4)
1.2.2 NFET to PFET Length Tracking	10	(1)
1.2.3 Channel Width Effects	11	(2)
1.2.4 Device Threshold Voltage Variation	13	(1)
1.2.5 Mobile Charge	13	(2)
1.2.6 Hot Carriers	15	(4)
1.2.7 Drain Resistance Modulation	19	(1)
1.2.8 Negative Bias Temperature Instability (NBTI)	20	(1)
1.2.9 Body Effect	21	(1)
1.2.10 Other Process Parameters	22	(3)
1.3 Charge Loss Mechanisms	25	(11)
1.3.1 Subthreshold Leakage Currents	26	(1)
1.3.2 Junction Leakage	27	(2)
1.3.3 Field-induced Leakage Mechanisms	29	(1)
1.3.4 Alpha Particle and Cosmic Ray Interactions	30	(2)
1.3.5 Defect Leakage	32	(4)
1.4 Back-End-Of-Line Variability Considerations	36	(11)
1.4.1 Wire Resistance	38	(3)
1.4.2 Line Width/Space	41	(2)
1.4.3 Dielectric Thickness and Permittivity	43	(1)
1.4.4 Wire Thickness	44	(1)
1.4.5 Contact Resistance	45	(2)
1.5 Summary	47	(4)
CHAPTER 2 Non-Clocked Logic Styles	51	(40)
2.1 Introduction	51	(3)
2.2 Static CMOS Structures	54	(4)
2.2.1 Static Combinatorial CMOS Logic	55	(2)
2.2.2 Pulsed Static Logic (PS-CMOS)	57	(1)
2.3 DCVS Logic	58	(7)
2.3.1 Differential Cascode Voltage-Switched Logic (DCVSL)	59	(2)
2.3.2 Differential Split Level Logic (DSL)	61	(2)
2.3.3 Cascode Non-Threshold Logic (CNTL)	63	(1)
2.3.4 DCVS Circuit Family Process Sensitivities	64	(1)
2.4 Non-Clocked Pass-Gate Families	65	(21)
2.4.1 CMOS Pass Gate (PG) and Transmission Gate (TG) Logic	68	(3)
2.4.2 DCVS Logic with the Pass Gate (DCVSPG)	71	(2)
2.4.3 Complementary Pass Gate Logic (CPL)	73	(3)
2.4.4 Swing-Restored Pass Gate Logic (SRPL)	76	(2)
2.4.5 Energy-Economized Pass Transistor Logic (EEPL)	78	(1)
2.4.6 Push-pull Pass transistor Logic (PPL)	79	(2)
2.4.7 Single-Ended Pass-Gate Logic (LEAP)	81	(3)
2.4.8 Double Pass-Transistor Logic (DPL)	84	(1)
2.4.9 Pass-Gate Circuit Family Process Sensitivities	85	(1)
2.5 Summary	86	(5)
CHAPTER 3 Clocked Logic Styles	91	(42)
3.1 Introduction	91	(2)
3.2 Single-Rail Domino Logic Styles	93	(14)
3.2.1 Domino CMOS	93	(5)
3.2.2 Multiple Output Domino Logic (MODL)	98	(2)
3.2.3 Compound Domino Logic	100	(1)
3.2.4 Noise Tolerant Precharge Logic (NTP)	101	(1)
3.2.5 Clock-Delayed Domino (CD Domino)	102	(2)
3.2.6 Self-Resetting Domino (SRCMOS)	104	(3)
3.3 Alternating-Polarity Domino Approaches	107	(4)
3.3.1 NORA	108	(2)
3.3.2 Zipper Domino	110	(1)
3.4 Dual-Rail Domino Structures	111	(6)
3.4.1 Differential Domino	111	(1)
3.4.2 Cross-Coupled Domino	112	(2)
3.4.3 Modified Dual-Rail Domino (MDDCVSL)	114	(1)
3.4.4 Dynamic Differential Split Level Logic (DDSL)	115	(1)
3.4.5 Pseudo-Clocked Domino	115	(2)
3.5 Latched Domino Structures	117	(7)
3.5.1 Sample-Set Diffential Logic (SSDL)	117	(2)
3.5.2 Enable/Disable CMOS Differential Logic (ECDL)	119	(2)
3.5.3 Latch Domino (LDomino)	121	(1)
3.5.4 Differential Current Switch Logic (DCSL)	122	(1)
3.5.5 Switched Output Differential Structure (SODS)	123	(1)
3.6 Clocked Pass-Gate Logic	124	(4)
3.6.1 Dynamic Complementary Pass Gate Logic (DCPL)	125	(2)
3.6.2 Sense-Amplifying Pipeline Flip-Flop (SA-F/F) Scheme	127	(1)
3.7 Summary	128	(5)
CHAPTER 4 Circuit Design Margin and Design Variability	133	(42)
4.1 Introduction	133	(1)
4.2 Process Induced Variation	134	(15)
4.2.1 Static CMOS Logic	134	(5)
4.2.2 Dynamic Domino Logic	139	(4)
4.2.3 Pass Gate Logic	143	(4)
4.2.4 Differential Cascode Voltage Switch Logic (DCVS)	147	(2)
4.3 Design Induced Variation	149	(4)
4.3.1 Intermediate Charge and Charge Sharing	149	(1)
4.3.2 Timing Collisions	150	(1)
4.3.3 Data Dependent Capacitance	151	(1)
4.3.4 Die Size Consideration	152	(1)
4.4 Application Induced Variation	153	(4)
4.4.1 VDD Tolerance Effects	153	(3)
4.4.2 Temperature Tolerance Effects	156	(1)
4.5 Noise	157	(12)
4.5.1 Capacitive Coupling (Crosstalk)	157	(2)
4.5.2 Delay Noise	159	(1)
4.5.3 Logic Noise	160	(7)
4.5.4 Transmission Lines	167	(1)
4.5.5 Simultaneous Switching	167	(1)
4.5.6 Soft Errors	168	(1)
4.6 Design Margin Budgeting	169	(2)
4.7 Summary	171	(4)
CHAPTER 5 Latching Strategies	175	(32)
5.1 Introduction	175	(2)
5.2 Basic Latch Design	177	(7)
5.2.1 Storage Elements	177	(2)
5.2.2 Static and Dynamic Latches	179	(1)
5.2.3 Latch Clocking	180	(2)
5.2.4 Noise/Robust Design	182	(2)
5.2.5 Latch Implementation	184	(1)
5.3 Latching Single-Ended Logic	184	(7)
5.3.1 pseudo Inverter Latch	185	(1)
5.3.2 True Single Phase Clocking (TSPC)	186	(3)
5.3.3 Double-Edge-Triggered Flip-Flops (DETFF	189	(2)
5.4 Latching Differential Logic	191	(5)
5.4.1 DCVS Latches	191	(1)
5.4.2 Static Ram Latches	192	(1)
5.4.3 Ratio Insensitive Differential Latch	193	(1)
5.4.4 Differential Flip-Flops	194	(2)
5.5 Race Free Latches for Precharged Logic	196	(4)
5.5.1 Cross-Coupled Differential Output	197	(1)
5.5.2 Negative Setup Pipeline Latch	198	(2)
5.6 Asynchronous Latch Techniques	200	(4)
5.6.1 SRCMOS Latch	200	(2)
5.6.2 Muller C-element	202	(1)
5.6.3 Asynchronous TSPC ETL	203	(1)
5.7 Summary	204	(3)
CHAPTER 6 Interface Techniques	207	(40)
6.1 Introduction	207	(3)
6.2 Signaling Standards	210	(2)
6.3 Chip-to-chip Communication Networks	212	(7)
6.4 ESD Protection	219	(3)
6.5 Driver Design Techniques	222	(12)
6.6 Receiver Design Techniques	234	(8)
6.7 Summary	242	(5)
CHAPTER 7 Clocking Styles	247	(38)
7.1 Introduction	247	(1)
7.2 Clock Jitter and Skew	248	(4)
7.2.1 Clock Jitter	248	(1)
7.2.2 Clock Skew	249	(1)
7.2.3 Total Clock Inaccuracy	249	(2)
7.2.4 Clocks and Noise Generation	251	(1)
7.3 Clock Generation	252	(3)
7.3.1 PLL Based Designs	252	(1)
7.3.2 Off-Chip Oscillator Based Design	253	(1)
7.3.3 Delay Locked Loops	254	(1)
7.3.4 Phase Splitters	254	(1)
7.3.5 Clock Chopping	255	(1)
7.4 Clock Distribution	255	(18)
7.4.1 Clock Distribution Techniques	258	(1)
7.4.2 Distributed buffers, placement optimization and standard wiring	258	(1)
7.4.3 Water-main Clock Distribution Technique	258	(1)
7.4.4 H-Tree Clock Distribution Technique	259	(3)
7.4.5 Grid Clock Distribution Technique	262	(1)
7.4.6 Length matched serpentines	262	(1)
7.4.7 Hybrid Clock Distribution Techniques	263	(1)
7.4.8 Comparison of the Industry's Best Clock Distribution Networks	263	(1)
7.4.9 Network Topologies	264	(1)
7.4.10 Grids	265	(2)
7.4.11 Trees	267	(1)
7.4.12 Length-Matched Serpentines	268	(1)
7.4.13 Comparisons	269	(1)
7.4.14 A 400 MHz Clock Tree Design	270	(2)
7.4.15 Clock Distribution Techniques Summary	272	(1)
7.5 Single Phase Clocking	273	(7)
7.5.1 Single-Phase Master-Slave Design	273	(3)
7.5.2 Single Phase Separated Latch Design	276	(2)
7.5.3 Clock Activates Logic and Opens Subsequent Latch	278	(1)
7.5.4 Clock Opens Latch and Activates Subsequent Logic	278	(2)
7.5.5 Single Phase Continuously Latching Design	280	(1)
7.6 Multi-Phase Clocking	280	(1)
7.6.1 Two Phase Clocking	281	(1)
7.6.2 Four Phase Strategies	281	(1)
7.7 Asynchronous Techniques	281	(1)
7.8 Summary	282	(3)
CHAPTER 8 Slack Borrowing and Time Stealing	285	(50)
8.1 Introduction	285	(1)
8.2 Slack Borrowing	286	(26)
8.2.1 Slack Borrowing in Symmetric 50% Duty Cycle 2-Phase Systems	288	(13)
8.2.2 Phase Partitioning in Symmetric 50% Duty Cycle 2-Phase Systems	301	(4)
8.2.3 Slack Borrowing and Phase Partitioning in Asymmetric 2-Phase Systems	305	(1)
8.2.4 Slack Borrowing Examples	306	(4)
8.2.5 Looping Effects on Slack Borrowing	310	(2)
8.3 Time Stealing	312	(21)
8.3.1 Time Stealing for Dynamic Logic in Symmetric 50% Duty Cycle 2-Phase Non-Overlapping Systems	314	(10)
8.3.2 Time Stealing for Dynamic Logic in Symmetric 2-Phase Overlapping Systems	324	(2)
8.3.3 Time Stealing for Dynamic Logic in Asymmetric 2-Phase Systems	326	(1)
8.3.4 Time Stealing in Master-Slave Systems	326	(4)
8.3.5 Time Stealing from a Previous Cycle or Phase	330	(2)
8.3.6 Looping Effects on Time Stealing	332	(1)
8.4 Summary	333	(2)
CHAPTER 9 Future Technology	335	(12)
9.1 Introduction	335	(1)
9.2 Classical Scaling Theory	335	(2)
9.3 Industry Trends Define Scaling Law	337	(1)
9.3.1 De-Facto Scaling	337	(1)
9.4 Challenges Presented by I/S Scaling	338	(2)
9.4.1 VT non-scaling	338	(1)
9.4.2 Gate Lithography	339	(1)
9.4.3 Gate Dielectric	339	(1)
9.4.4 Interconnect Delays and Noise	340	(1)
9.5 Possible Directions	340	(7)
INDEX	347