High-Speed Signaling Jitter Modeling, Analysis, and Budgeting

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  • Edition: 1st
  • Format: Hardcover
  • Copyright: 2011-10-06
  • Publisher: Prentice Hall
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As data communication rates accelerate well into the multi-gigahertz range, ensuring signal integrity both on- and off-chip has become crucial, and high-speed signal integrity engineering has grown into one of today's most important engineering disciplines. This book brings together cutting-edge contributions from the field's most respected practitioners and researchers, including leaders at Rambus, MIT, and the University of California, Berkeley. Edited by pioneering experts Dan Oh and Chuck Yuan, these contributors illuminate the newest design challenges in signal integrity and power integrity (SI/PI). They summarize emerging issues and new modeling/analysis methodologies used by leading companies such as Rambus, Intel, and IBM; and thoroughly cover high-speed signaling analysis, including signal and power integrity with on-chip device jitter. Throughout, this book focuses on understanding the "big picture" - now essential to predicting overall link performance. You will find innovative modeling and design methodologies for high-speed signaling, including statistical link simulation; experiment design; signal conditioning (EQ); modeling on-chip noise; modeling random and power-supply noise; on-chip measurement, and more. Published and validated in numerous conferences and journals, all these techniques are now described in detail in easy-to-read book format for the first time.

Author Biography

Kyung Suk (Dan) Oh, Senior Principal Engineer at Rambus Inc., leads signal integrity analysis and tool development for products including serial, parallel, and memory interfaces. His interests include advanced SI/PI modeling and simulation, channel design optimization for I/O links, and application of signaling techniques to high-speed digital links. He has published more than 70 papers and holds seven U.S. patents and ten pending patent applications. Dr. Oh serves on IEEE's EPEPS technical program committee. Xingchao (Chuck) Yuan, Director of Design Engineering at Rambus, is responsible for designing Rambus's multi-gigahertz signaling technologies for graphics and main memory applications. He has published more than 100 papers and holds eight U.S. patents. His team's work led to Rambus's advanced XDR memory architecture, which has been adopted in a number of applications including the PlayStation3, DLP projectors, and DTVs. He is an IEEE senior member.

Table of Contents

Prefacep. viii
Introductionp. 1
Signal Integrity Analysis Trendsp. 4
Challenges of High-Speed Signal Integrity Designp. 8
Organization of This Bookp. 9
Referencesp. 11
High-Speed Signaling Basicsp. 13
I/O Signaling Basics and Componentsp. 13
Noise Sourcesp. 24
Jitter Basics and Decompositionsp. 33
Summaryp. 39
Referencesp. 39
Channel Modeling and Designp. 41
Channel Modeling and Design Methodologyp. 43
Channel Design Methodologyp. 44
Channel Modeling Methodologyp. 49
Modeling with Electromagnetic Field Solversp. 52
Backplane Channel Modeling Examplep. 54
Summaryp. 63
Referencesp. 64
Network Parametersp. 65
Generalized Network Parameters for Multi-Conductor Systemsp. 66
Preparing an Accurate S-Parameter Time-Domain Modelp. 77
Passivity Conditionsp. 85
Causality Conditionsp. 89
Summaryp. 98
Referencesp. 101
Transmission Linesp. 103
Transmission Line Theoryp. 104
Forward and Backward Crosstalkp. 109
Time-Domain Simulation of Transmission Linesp. 115
Modeling Transmission Line from Measurementsp. 121
On-Chip Wire Modelingp. 136
Comparison of On-Chip, Package, and PCB Tracesp. 142
Summaryp. 145
Referencesp. 145
Analyzing Link Performancep. 151
Channel Voltage and Timing Budgetp. 153
Timing Budget Equation and Componentsp. 155
Fibre Channel Dual-Dirac Modelp. 156
Component-Level Timing Budgetp. 160
Pitfalls of Timing Budget Equationp. 161
Voltage Budget Equations and Componentsp. 164
Summaryp. 165
Referencesp. 165
Manufacturing Variation Modelingp. 167
Introduction to the Taguchi Methodp. 168
DDR DRAM Command/Address Channel Examplep. 179
Backplane Link Modeling Examplep. 186
Summaryp. 192
Appendixp. 193
Referencesp. 196
Link BER Modeling and Simulationp. 197
Historical Background and Chapter Organizationp. 198
Statistical Link BER Modeling Frameworkp. 199
Intersymbol Interference Modelingp. 206
Transmitter and Receiver Jitter Modelingp. 210
Periodic Jitter Modelingp. 218
Summaryp. 225
Referencesp. 226
Fast Time-Domain Channel Simulation Techniquesp. 229
Fast Time-Domain Simulation Flow Overviewp. 230
Fast System Simulation Techniquesp. 232
Simultaneous Switching Noise Examplep. 245
Comparison of Jitter Modeling Methodsp. 246
Peak Distortion Analysisp. 248
Summaryp. 253
Referencesp. 253
Clock Models in Link BER Analysisp. 257
Independent and Common Clock Jitter Modelsp. 258
Modeling Common Clocking Schemesp. 259
CDR Circuitry Modelingp. 268
Passive Channel JIF and Jitter Amplificationp. 273
Summaryp. 277
Referencesp. 277
Supply Noise and Jitterp. 279
Overview of Power Integrity Engineeringp. 281
PDN Design Goals and Supply Budgetp. 282
Power Supply Budget Componentsp. 283
Deriving a Power Supply Budgetp. 287
Supply Noise Analysis Methodologyp. 290
Steps in Power Supply Noise Analysisp. 294
Summaryp. 300
Referencesp. 301
SSN Modeling and Simulationp. 303
SSN Modeling Challengesp. 305
SI and PI Co-Simulation Methodologyp. 310
Signal Current Loop and Supply Noisep. 321
Additional SSN Modeling Topicsp. 325
Case Study: DDR2 SSN Analysis for Consumer Applicationsp. 330
Summaryp. 336
Referencesp. 337
SSN Reduction Codes and Signalingp. 339
Data Bus Inversion Codep. 340
Pseudo Differential Signaling Based on 4b6b Codep. 346
Summaryp. 357
Referencesp. 357
Supply Noise and Jitter Characterizationp. 359
Importance of Supply Noise Induced Jitterp. 360
Overview of PSIJ Modeling Methodologyp. 361
Noise and Jitter Simulation Methodologyp. 364
Case Studyp. 372
Summaryp. 376
Referencesp. 377
Substrate Noise Induced Jitterp. 379
Introductionp. 380
Modeling Techniquesp. 382
Measurement Techniquesp. 391
Case Studyp. 393
Summaryp. 400
Referencesp. 400
Advanced Topicsp. 403
On-Chip Link Measurement Techniquesp. 405
Shmoo and BER Eye Diagram Measurementsp. 407
Capturing Signal Waveformsp. 408
Link Performance Measurement and Correlationp. 411
On-Chip Supply Noise Measurement Techniquesp. 412
Advanced Power Integrity Measurementsp. 418
Summaryp. 422
Referencesp. 423
Signal Conditioningp. 425
Single-Bit Responsep. 426
Equalization Techniquesp. 427
Equalization Adaptation Algorithmsp. 433
CDR and Equalization Adaptation Interactionp. 442
ADC-Based Receive Equalizationp. 445
Future of High-Speed Wireline Equalizationp. 448
Summaryp. 449
Referencesp. 450
Applicationsp. 455
XDR: High-Performance Differential Memory Systemp. 456
Mobile XDR: Low Power Differential Memory Systemp. 465
Main Memory Systems beyond DDR3p. 476
Future Signaling Systemsp. 486
Referencesp. 491
Indexp. 495
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