High-Speed Signaling Jitter Modeling, Analysis, and Budgeting

by Oh, Kyung Suk (Dan); Yuan, Xing Chao (Chuck)

• ISBN13: 9780132826914
• ISBN10: 0132826917
• Edition: 1st
• Format: Hardcover
• Copyright: 2011-10-06
• Publisher: Prentice Hall

Summary

As data communication rates accelerate well into the multi-gigahertz range, ensuring signal integrity both on- and off-chip has become crucial, and high-speed signal integrity engineering has grown into one of today's most important engineering disciplines. This book brings together cutting-edge contributions from the field's most respected practitioners and researchers, including leaders at Rambus, MIT, and the University of California, Berkeley. Edited by pioneering experts Dan Oh and Chuck Yuan, these contributors illuminate the newest design challenges in signal integrity and power integrity (SI/PI). They summarize emerging issues and new modeling/analysis methodologies used by leading companies such as Rambus, Intel, and IBM; and thoroughly cover high-speed signaling analysis, including signal and power integrity with on-chip device jitter. Throughout, this book focuses on understanding the "big picture" - now essential to predicting overall link performance. You will find innovative modeling and design methodologies for high-speed signaling, including statistical link simulation; experiment design; signal conditioning (EQ); modeling on-chip noise; modeling random and power-supply noise; on-chip measurement, and more. Published and validated in numerous conferences and journals, all these techniques are now described in detail in easy-to-read book format for the first time.

Author Biography

Kyung Suk (Dan) Oh, Senior Principal Engineer at Rambus Inc., leads signal integrity analysis and tool development for products including serial, parallel, and memory interfaces. His interests include advanced SI/PI modeling and simulation, channel design optimization for I/O links, and application of signaling techniques to high-speed digital links. He has published more than 70 papers and holds seven U.S. patents and ten pending patent applications. Dr. Oh serves on IEEE's EPEPS technical program committee. Xingchao (Chuck) Yuan, Director of Design Engineering at Rambus, is responsible for designing Rambus's multi-gigahertz signaling technologies for graphics and main memory applications. He has published more than 100 papers and holds eight U.S. patents. His team's work led to Rambus's advanced XDR memory architecture, which has been adopted in a number of applications including the PlayStation3, DLP projectors, and DTVs. He is an IEEE senior member.

Table of Contents

Preface	p. viii
Introduction	p. 1
Signal Integrity Analysis Trends	p. 4
Challenges of High-Speed Signal Integrity Design	p. 8
Organization of This Book	p. 9
References	p. 11
High-Speed Signaling Basics	p. 13
I/O Signaling Basics and Components	p. 13
Noise Sources	p. 24
Jitter Basics and Decompositions	p. 33
Summary	p. 39
References	p. 39
Channel Modeling and Design	p. 41
Channel Modeling and Design Methodology	p. 43
Channel Design Methodology	p. 44
Channel Modeling Methodology	p. 49
Modeling with Electromagnetic Field Solvers	p. 52
Backplane Channel Modeling Example	p. 54
Summary	p. 63
References	p. 64
Network Parameters	p. 65
Generalized Network Parameters for Multi-Conductor Systems	p. 66
Preparing an Accurate S-Parameter Time-Domain Model	p. 77
Passivity Conditions	p. 85
Causality Conditions	p. 89
Summary	p. 98
References	p. 101
Transmission Lines	p. 103
Transmission Line Theory	p. 104
Forward and Backward Crosstalk	p. 109
Time-Domain Simulation of Transmission Lines	p. 115
Modeling Transmission Line from Measurements	p. 121
On-Chip Wire Modeling	p. 136
Comparison of On-Chip, Package, and PCB Traces	p. 142
Summary	p. 145
References	p. 145
Analyzing Link Performance	p. 151
Channel Voltage and Timing Budget	p. 153
Timing Budget Equation and Components	p. 155
Fibre Channel Dual-Dirac Model	p. 156
Component-Level Timing Budget	p. 160
Pitfalls of Timing Budget Equation	p. 161
Voltage Budget Equations and Components	p. 164
Summary	p. 165
References	p. 165
Manufacturing Variation Modeling	p. 167
Introduction to the Taguchi Method	p. 168
DDR DRAM Command/Address Channel Example	p. 179
Backplane Link Modeling Example	p. 186
Summary	p. 192
Appendix	p. 193
References	p. 196
Link BER Modeling and Simulation	p. 197
Historical Background and Chapter Organization	p. 198
Statistical Link BER Modeling Framework	p. 199
Intersymbol Interference Modeling	p. 206
Transmitter and Receiver Jitter Modeling	p. 210
Periodic Jitter Modeling	p. 218
Summary	p. 225
References	p. 226
Fast Time-Domain Channel Simulation Techniques	p. 229
Fast Time-Domain Simulation Flow Overview	p. 230
Fast System Simulation Techniques	p. 232
Simultaneous Switching Noise Example	p. 245
Comparison of Jitter Modeling Methods	p. 246
Peak Distortion Analysis	p. 248
Summary	p. 253
References	p. 253
Clock Models in Link BER Analysis	p. 257
Independent and Common Clock Jitter Models	p. 258
Modeling Common Clocking Schemes	p. 259
CDR Circuitry Modeling	p. 268
Passive Channel JIF and Jitter Amplification	p. 273
Summary	p. 277
References	p. 277
Supply Noise and Jitter	p. 279
Overview of Power Integrity Engineering	p. 281
PDN Design Goals and Supply Budget	p. 282
Power Supply Budget Components	p. 283
Deriving a Power Supply Budget	p. 287
Supply Noise Analysis Methodology	p. 290
Steps in Power Supply Noise Analysis	p. 294
Summary	p. 300
References	p. 301
SSN Modeling and Simulation	p. 303
SSN Modeling Challenges	p. 305
SI and PI Co-Simulation Methodology	p. 310
Signal Current Loop and Supply Noise	p. 321
Additional SSN Modeling Topics	p. 325
Case Study: DDR2 SSN Analysis for Consumer Applications	p. 330
Summary	p. 336
References	p. 337
SSN Reduction Codes and Signaling	p. 339
Data Bus Inversion Code	p. 340
Pseudo Differential Signaling Based on 4b6b Code	p. 346
Summary	p. 357
References	p. 357
Supply Noise and Jitter Characterization	p. 359
Importance of Supply Noise Induced Jitter	p. 360
Overview of PSIJ Modeling Methodology	p. 361
Noise and Jitter Simulation Methodology	p. 364
Case Study	p. 372
Summary	p. 376
References	p. 377
Substrate Noise Induced Jitter	p. 379
Introduction	p. 380
Modeling Techniques	p. 382
Measurement Techniques	p. 391
Case Study	p. 393
Summary	p. 400
References	p. 400
Advanced Topics	p. 403
On-Chip Link Measurement Techniques	p. 405
Shmoo and BER Eye Diagram Measurements	p. 407
Capturing Signal Waveforms	p. 408
Link Performance Measurement and Correlation	p. 411
On-Chip Supply Noise Measurement Techniques	p. 412
Advanced Power Integrity Measurements	p. 418
Summary	p. 422
References	p. 423
Signal Conditioning	p. 425
Single-Bit Response	p. 426
Equalization Techniques	p. 427
Equalization Adaptation Algorithms	p. 433
CDR and Equalization Adaptation Interaction	p. 442
ADC-Based Receive Equalization	p. 445
Future of High-Speed Wireline Equalization	p. 448
Summary	p. 449
References	p. 450
Applications	p. 455
XDR: High-Performance Differential Memory System	p. 456
Mobile XDR: Low Power Differential Memory System	p. 465
Main Memory Systems beyond DDR3	p. 476
Future Signaling Systems	p. 486
References	p. 491
Index	p. 495
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