9780131247116

Logic and Computer Design Fundamentals and Xilinx Student Edition 4.2 Package

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  • ISBN13:

    9780131247116

  • ISBN10:

    0131247115

  • Edition: 3rd
  • Format: Package
  • Copyright: 2004-01-01
  • Publisher: PRENTICE-HALL
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Supplemental Materials

What is included with this book?

Summary

For one- to two-semester Computer Science and Engineering courses in logic and digital design at the sophomore/junior level. Featuring a strong emphasis on the fundamentals underlying contemporary logic design using hardware description languages, synthesis, and verification, this book focuses on the ever-evolving applications of basic computer design concepts with strong connections to real-world technology.

Table of Contents

Preface xiii
Chapter 1 DIGITAL COMPUTERS AND INFORMATION 3(26)
1-1 Digital Computers
3(5)
Information Representation
5(1)
Computer Structure
6(1)
More on the Generic Computer
6(2)
1-2 Number Systems
8(5)
Binary Numbers
9(2)
Octal and Hexadecimal Numbers
11(2)
Number Ranges
13(1)
1-3 Arithmetic Operations
13(5)
Conversion from Decimal to Other Bases
16(2)
1-4 Decimal Codes
18(3)
BCD Addition
19(1)
Parity Bit
20(1)
1-5 Gray Codes
21(2)
1-6 Alphanumeric Codes
23(2)
ASCII Character Code
24(1)
1-7 Chapter Summary
25(4)
References
26(1)
Problems
26(3)
Chapter 2 COMBINATIONAL LOGIC CIRCUITS 29(58)
2-1 Binary Logic and Gates
29(4)
Binary Logic
30(2)
Logic Gates
32(1)
2-2 Boolean Algebra
33(8)
Basic Identities of Boolean Algebra
35(2)
Algebraic Manipulation
37(3)
Complement of a Function
40(1)
2-3 Standard Forms
41(6)
Minterms and Maxterms
42(3)
Sum of Products
45(1)
Product of Sums
46(1)
2-4 Two-Level Circuit Optimization
47(11)
Cost Criteria
48(1)
Two-Variable Map
49(1)
Three-Variable Map
50(5)
Four-Variable Map
55(3)
2-5 Map Manipulation
58(7)
Essential Prime Implicant
59(2)
Nonessential Prime Implicants
61(1)
Product-of-Sums Optimization
62(1)
Don't-Care Conditions
63(2)
2-6 Multiple-Level Circuit Optimization
65(5)
2-7 Other Gate Types
70(5)
2-8 Exclusive-OR Operator and Gates
75(5)
Odd Function
76(4)
2-9 High-Impedance Outputs
2-10 Chapter Summary
80(7)
References
80(1)
Problems
81(6)
Chapter 3 COMBINATIONAL LOGIC DESIGN 87(54)
3-1 Design Concepts and Automation
87(9)
Design Hierarchy
89(3)
Top-Down Design
92(1)
Computer-Aided Design
92(1)
Hardware Description Languages
93(2)
Logic Synthesis
95(1)
3-2 The Design Space
96(8)
Gate Properties
97(1)
Levels of Integration
97(1)
Circuit Technologies
97(1)
Technology Parameters
98(3)
Positive and Negative Logic
101(2)
Design Trade-Offs
103(1)
3-3 Design Procedure
104(6)
3-4 Technology Mapping
110(11)
Cell Specification
112(1)
Libraries
112(1)
Mapping Techniques
113(8)
3-5 Verification
121(3)
Manual Logic Analysis
121(1)
Simulation
122(2)
3-6 Programmable Implementation Technologies
124(8)
Read-Only Memory
127(2)
Programmable Logic Array
129(1)
Programmable Array Logic Devices
130(2)
3-7 Chapter Summary
132(9)
References
133(1)
Problems
133(8)
Chapter 4 COMBINATIONAL FUNCTIONS AND CIRCUITS 141(60)
4-1 Combinational Circuits
141(1)
4-2 Rudimentary Logic Functions
142(5)
Value-Fixing, Transferring, and Inverting
142(1)
Multiple-Bit Functions
143(3)
Enabling
146(1)
4-3 Decoding
147(5)
Decoder Expansion
148(3)
Decoder and Enabling Combinations
151(1)
4-4 Encoding
152(4)
Priority Encoder
153(2)
Encoder Expansion
155(1)
4-5 Selecting
156(5)
Multiplexers
156(2)
Multiplexer Expansion
158(1)
Alternative Selection Implementations
159(2)
4-6 Combinational Function Implementation
161(15)
Using Decoders
162(2)
Using Multiplexers
164(2)
Using Read-Only Memories
166(3)
Using Programmable Logic Arrays
169(2)
Using Programmable Array Logic Devices
171(4)
Using Lookup Tables
175(1)
4-7 HDL Representation for Combinational Circuits-VHDL
176(8)
4-8 HDL Representations for Combinational Circuits-Verilog
184(6)
4-9 Chapter Summary
190(11)
References
191(1)
Problems
191(10)
Chapter 5 ARITHMETIC FUNCTIONS AND CIRCUITS 201(40)
5-1 Iterative Combinational Circuits
201(1)
5-2 Binary Adders
202(8)
Half Adder
203(1)
Full Adder
204(1)
Binary Ripple Carry Adder
205(1)
Carry Lookahead Adder
206(4)
5-3 Binary Subtraction
210(5)
Complements
212(1)
Subtraction with Complements
213(2)
5-4 Binary Adder-Subtractors
215(6)
Signed Binary Numbers
216(2)
Signed Binary Addition and Subtraction
218(2)
Overflow
220(1)
5-5 Binary Multiplication
221(2)
5-6 Other Arithmetic Functions
223(6)
Contraction
224(1)
Incrementing
225(1)
Decrementing
226(1)
Multiplication by Constants
227(1)
Division by Constants
227(1)
Zero Fill and Extension
227(2)
5-7 HDL Representations-VHDL
229(4)
Behavioral Description
231(2)
5-8 HDL Representations-Verilog
233(2)
Behavioral Description
234(1)
5-9 Chapter Summary
235(6)
References
235(1)
Problems
236(5)
Chapter 6 SEQUENTIAL CIRCUITS 241(68)
6-1 Sequential Circuit Definitions
242(2)
6-2 Latches
244(5)
SR and S R Latches
245(3)
D Latch
248(1)
6-3 Flip-Flops
249(9)
Master-Slave Flip-Flops
250(3)
Edge-Triggered Flip-Flop
253(1)
Standard Graphics Symbols
254(2)
Direct Inputs
256(1)
Flip-Flop Timing
257(1)
6-4 Sequential Circuit Analysis
258(9)
Input Equations
258(2)
State Table
260(2)
State Diagram
262(1)
Sequential Circuit Timing
263(3)
Simulation
266(1)
6-5 Sequential Circuit Design
267(14)
Design Procedure
268(1)
Finding State Diagrams and State Tables
268(7)
State Assignment
275(1)
Designing with D Flip-Flops
275(2)
Designing with Unused States
277(2)
Verification
279(2)
6-6 Other Flip-Flop Types
281(3)
JK and T Flip-Flops
282(2)
6-7 HDL Representation for Sequential Circuits-VHDL
284(7)
6-8 HDL Representation for Sequential Circuits-Verilog
291(7)
6-9 Chapter Summary
298(11)
References
299(1)
Problems
299(10)
Chapter 7 REGISTERS AND REGISTER TRANSFERS 309(54)
7-1 Registers and Load Enable
310(3)
Register with Parallel Load
311(2)
7-2 Register Transfers
313(2)
7-3 Register Transfer Operations
315(3)
7-4 A Note for VHDL and Verilog Users Only
318(1)
7-5 Microoperations
318(6)
Arithmetic Microoperations
319(2)
Logic Microoperations
321(2)
Shift Microoperations
323(1)
7-6 Microoperations on a Single Register
324(15)
Multiplexer-Based Transfers
324(2)
Shift Registers
326(5)
Ripple Counter
331(2)
Synchronous Binary Counters
333(4)
Other Counters
337(2)
7-7 Register Cell Design
339(6)
7-8 Multiplexer and Bus-Based Transfers for Multiple Registers
345(3)
Three-State Bus
346(2)
7-9 Serial Transfer and Microoperations
348(3)
Serial Addition
349(2)
7-10 HDL Representation for Shift Registers and Counters -VHDL
351(2)
7-11 HDL Representation for Shift Registers and Counters-Verilog
353(1)
7-12 Chapter Summary
354(9)
References
356(1)
Problems
356(7)
Chapter 8 SEQUENCING AND CONTROL 363(36)
8-1 The Control Unit
364(1)
8-2 Algorithmic State Machines
365(4)
The ASM Chart
365(3)
Timing Considerations
368(1)
8-3 ASM Chart Examples
369(6)
Binary Multiplier
369(6)
8-4 Hardwired Control
375(9)
Sequence Register and Decoder
378(2)
One Flip-Flop per State
380(4)
8-5 HDL Representation of the Binary Multiplier-VHDL
384(3)
8-6 HDL Representation of the Binary Multiplier Verilog
387(3)
8-7 Microprogrammed Control
390(2)
8-8 Chapter Summary
392(7)
References
392(1)
Problems
393(6)
Chapter 9 MEMORY BASICS 399(30)
9-1 Memory Definitions
399(1)
9-2 Random-Access Memory
400(5)
Write and Read Operations
402(1)
Timing Waveforms
402(3)
Properties of Memory
405(1)
9-3 SRAM Integrated Circuits
405(6)
Coincident Selection
408(3)
9-4 Array of SRAM ICs
411(4)
9-5 DRAM ICs
415(6)
DRAM Cell
415(2)
DRAM Bit Slice
417(4)
9-6 DRAM Types
421(5)
Synchronous DRAM (SDRAM)
421(3)
Double Data Rate SDRAM (DDR SDRAM)
424(1)
RAMBUSĀ® DRAM (RDRAM)
425(1)
9-7 Arrays of Dynamic RAM ICs
426(1)
9-8 Chapter Summary
426(3)
References
427(1)
Problems
427(2)
Chapter 10 COMPUTER DESIGN BASICS 429(54)
10-1 Introduction
430(1)
10-2 Datapaths
430(3)
10-3 The Arithmetic/Logic Unit
433(6)
Arithmetic Circuit
434(3)
Logic Circuit
437(1)
Arithmetic/Logic Unit
437(2)
10-4 The Shifter
439(2)
Barrel Shifter
440(1)
10-5 Datapath Representation
441(3)
10-6 The Control Word
444(5)
10-7 A Simple Computer Architecture
449(7)
Instruction Set Architecture
450(1)
Storage Resources
450(1)
Instruction Formats
451(3)
Instruction Specifications
454(2)
10-8 Single-Cycle Hardwired Control
456(8)
Instruction Decoder
458(2)
Sample Instructions and Program
460(2)
Single-Cycle Computer Issues
462(2)
10-9 Multiple-Cycle Hardwired Control
464(11)
Sequential Control Design
467(8)
10-10 Chapter Summary
475(8)
References
475(1)
Problems
476(7)
Chapter 11 INSTRUCTION SET ARCHITECTURE 483(44)
11-1 Computer Architecture Concepts
483(2)
Basic Computer Operation Cycle
484(1)
Register Set
485(1)
11-2 Operand Addressing
485(7)
Three-Address Instructions
486(1)
Two-Address Instructions
487(1)
One-Address Instruction
487(1)
Zero-Address Instructions
488(1)
Addressing Architectures
489(3)
11-3 Addressing Modes
492(7)
Implied Mode
493(1)
Immediate Mode
493(1)
Register and Register-Indirect
493(1)
Modes Direct Addressing Mode
494(2)
Indirect Addressing Mode
496(1)
Relative Addressing Mode
496(1)
Indexed Addressing Mode
496(1)
Summary of Addressing Modes
497(2)
11-4 Instruction Set Architectures
499(1)
11-5 Data Transfer Instructions
500(3)
Stack Instructions
501(1)
Independent versus Memory-Mapped I/O
502(1)
11-6 Data Manipulation Instructions
503(4)
Arithmetic Instructions
504(1)
Logical and Bit Manipulation Instructions
505(1)
Shift Instructions
506(1)
11-7 Floating-Point Computations
507(5)
Arithmetic Operations
508(1)
Biased Exponent
509(1)
Standard Operand Format
510(2)
11-8 Program Control Instructions
512(5)
Conditional Branch Instructions
513(3)
Procedure Call and Return Instructions
516(1)
11-9 Program Interrupt
517(7)
Types of Interrupts
518(1)
Processing External Interrupts
519(5)
11-10 Chapter Summary
524(3)
References
521(1)
Problems
522(5)
Chapter 12 RISC AND CISC CENTRAL PROCESSING UNITS 527(52)
12-1 Pipelined Datapath
527(6)
Execution of Pipeline
528(4)
Microoperations
532(1)
12-2 Pipelined Control
533(4)
Pipeline Programming and Performance
535(2)
12-3 The Reduced Instruction Set Computer
537(20)
Instruction Set Architecture
538(3)
Addressing Modes
541(1)
Datapath Organization
541(3)
Control Organization
544(2)
Data Hazards
546(7)
Control Hazards
553(4)
12-4 The Complex Instruction Set Computer
557(12)
ISA Modifications
559(1)
Datapath Modifications
560(2)
Control Unit Modifications
562(1)
Microprogrammed Control
563(3)
Microprograms for Complex Instructions
566(3)
12-5 More on Design
569(2)
High-Performance CPU Concepts
569(3)
Recent Architectural Innovations
572(1)
Digital Systems
573
12-6 Chapter Summary
571(8)
References
575(1)
Problems
575(4)
Chapter 13 INPUT-OUTPUT AND COMMUNICATION 579(38)
13-1 Computer I/O
579(1)
13-2 Sample Peripherals
580(4)
Keyboard
580(1)
Hard Disk
581(2)
Graphics Display
583(1)
I/O Transfer Rates
584(1)
13-3 I/O Interfaces
584(7)
I/O Bus and Interface Unit
585(1)
Example of I/O Interface
586(2)
Strobing
588(1)
Handshaking
589(2)
13-4 Serial Communication
591(7)
Asynchronous Transmission
592(1)
Synchronous Transmission
593(1)
The Keyboard Revisited
593(1)
A Packet-Based Serial I/O Bus
594(4)
13-5 Modes of Transfer
598(3)
Example of Program-Controlled Transfer
599(2)
Interrupt-Initiated Transfer
601(1)
13-6 Priority Interrupt
601(4)
Daisy Chain Priority
602(1)
Parallel Priority Hardware
603(2)
13-7 Direct Memory Access
605(4)
DMA Controller
606(2)
DMA Transfer
608(1)
13-8 I/O Processors
609(3)
13-9 Chapter Summary
612(5)
References
613(1)
Problems
613(4)
Chapter 14 MEMORY SYSTEMS 617(30)
14-1 Memory Hierarchy
618(2)
14-2 Locality of Reference
620(2)
14-3 Cache Memory
622(14)
Cache Mappings
624(5)
Line Size
629(2)
Cache Loading
631(1)
Write Methods
631(1)
Integration of Concepts
632(3)
Instruction and Data Caches
635(1)
Multiple-Level Caches
635(1)
14-4 Virtual Memory
636(6)
Page Tables
638(2)
Translation Lookaside Buffer
640(2)
Virtual Memory and Cache
642(1)
14-5 Chapter Summary
642(5)
References
643(1)
Problems
643(4)
INDEX 647

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