Low-Power NoC for High-Performance SoC Design

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  • Edition: 1st
  • Format: Hardcover
  • Copyright: 2008-03-31
  • Publisher: CRC Press

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Chip Design and Implementation from a Practical Viewpoint Focusing on chip implementation, Low-Power NoC for High-Performance SoC Designprovides practical knowledge and real examples of how to use network on chip (NoC) in the design of system on chip (SoC). It discusses many architectural and theoretical studies on NoCs, including design methodology, topology exploration, quality-of-service guarantee, low-power design, and implementation trials. The Steps to Implement NoC The book covers the full spectrum of the subject, from theory to actual chip design using NoC. Employing the Unified Modeling Language (UML) throughout, it presents complicated concepts, such as models of computation and communication'computation partitioning, in a manner accessible to laypeople. The authors provide guidelines on how to simplify complex networking theory to design a working chip. In addition, they explore the novel NoC techniques and implementations of theBasic On-Chip Network (BONE) project. Examples of real-time decisions, circuit-level design, systems, and chips give the material a real-world context. Low-Power NoC and Its Application to SoC Design Emphasizing the application of NoC to SoC design, this book shows how to build the complicated interconnections on SoC while keeping a low power consumption.

Table of Contents

Prefacep. xi
Authorsp. xiii
NoC-Based System-Level Design
NoC and System-Level Designp. 3
Introduction to SoC Designp. 3
System Model and Design Flowp. 6
System Analysis with UMLp. 9
Architecture Designp. 16
Platform-Based SoC Designp. 21
Concept of the Platformp. 21
Types of Platformsp. 24
Processor-Centric Platformp. 27
Application-Specific Platformp. 29
Fully Programmable Platformp. 30
Communication-Centric Platformp. 30
Multiprocessor SoC and Network on Chipp. 34
Concept of MPSoCp. 34
MPSoC and NoCp. 36
Low-Power SoC Designp. 37
CMOS Circuit-Level Low-Power Designp. 37
Architecture-Level Low-Power Designp. 40
System-Level Low-Power Designp. 41
Trends in Low-Power Designp. 43
Referencesp. 45
System Design with Model of Computationp. 47
System Modelsp. 47
Types of Modelsp. 48
Communicationp. 49
Behavior: Time and State Spacep. 49
Models of Computationp. 52
Finite State Machine and Its Variantsp. 52
Petri Netp. 54
Transaction-Level Modelingp. 55
Dataflow Graph and Its Variantsp. 57
Process Algebra-Based Semanticsp. 61
Summaryp. 62
Validation and Verificationp. 64
Simulationp. 65
Discrete-Event Simulationp. 66
Cycle-Based Simulationp. 66
Transaction-Level Simulationp. 68
Formal Methodp. 69
Referencesp. 71
Hardware/Software Codesignp. 73
Codesignp. 73
Application Analysisp. 77
Performance Indexp. 77
Task Graph: Sound Semantics for Application Analysisp. 79
Implementing Task Graph in Unified Modeling Language (UML)p. 83
Synthesisp. 89
Partitioning and Resource Allocationp. 89
Schedulingp. 99
Referencesp. 99
Computation-Communication Partitioningp. 101
Communication System: Current Trendp. 101
Separation of Communication and Computationp. 106
Communication-Centric SoC Designp. 107
Overviewp. 107
OCP-IP: Socket Abstractionp. 109
Communication Synthesisp. 111
High-Level Communication System Designp. 112
Communication Design Methodsp. 115
Network-Based Designp. 123
Referencesp. 127
NoC-Based Real Chip Implementation
Network on Chip-Based SoCp. 131
Network on Chipp. 131
NoC for SoC Designp. 131
Comparison of Bus-Based and NoC-Based SoC Designp. 133
OSI Seven-Layer NoC Modelp. 134
An Example of NoC-Based SoC Designp. 138
Architecture of NoCp. 139
Basic NoC Design Issuesp. 139
Design of NoC Building Blocksp. 142
High-Speed Signalingp. 142
Queue and Buffer Designp. 142
Switch Designp. 144
Scheduler Designp. 145
Practical Design of NoCp. 147
Topology Selectionp. 147
Routing Schemep. 148
Switching Schemep. 148
Phit Size Determinationp. 149
SERDES Designp. 151
Mesochronous Synchronizerp. 151
Referencesp. 154
NoC Topology and Protocol Designp. 157
Introductionp. 157
Analysis Methodologyp. 159
Topology Pool and Target Systemp. 159
NoC Traffic and Energy Modelsp. 160
Energy Explorationp. 162
Bus Topologyp. 162
Mesh Topologyp. 164
Star Topologyp. 166
Point-to-Point Topologyp. 166
Heterogeneous Topologiesp. 168
NoC Protocol Designp. 168
Layered Architecturep. 172
Physical Layer Protocolp. 173
Data Link Layer Protocolp. 175
Network Layer Protocolp. 176
Transport Layer Protocolp. 178
Multiple-Outstanding-Addressingp. 179
Write with Acknowledgep. 179
Burst Packet Transferp. 179
Enhanced Burst Packet Transferp. 181
Protocol Design with Finite State Machine Modelp. 182
Packet Design for NoCp. 183
Summaryp. 187
Referencesp. 187
Low-Power Design for NoCp. 189
Introductionp. 189
Low-Power Signalingp. 189
Channel Coding to Reduce the Switching Probability-[alpha]p. 190
Wire Capacitance Reducing Techniquesp. 191
Low-Swing Signalingp. 191
Driver Circuitsp. 191
Receiver Circuitsp. 191
Static and Dynamic Wiresp. 193
Optimal Voltage Swingp. 193
Frequency and Voltage Scalingp. 194
On-Chip Serializationp. 194
Area and Energy-Consumption Variation Due to the OCSp. 195
Optimal Serialization Ratiop. 196
Low-Power Clockingp. 197
Clock Distribution inside the NoCp. 197
Synchronizersp. 198
Low-Power Channel Codingp. 200
SILENT Codingp. 200
Performance Analysis of SILENT Codingp. 203
SILENT Coding for Multimedia Applicationsp. 205
Low-Power Switchp. 206
Low-Power Technique for Switch Fabricp. 206
Crossbar Partial Activation Techniquep. 206
Switch Schedulerp. 207
Low-Power Scheduler: Mux-Tree-Based Round-Robin Schedulerp. 208
Low-Power Network on Chip Protocolp. 210
Protocol Definitionp. 210
Protocol Compositionp. 210
Low-Power Issues on the NoC Protocolp. 211
Aligned Packet Formationp. 211
Packet Switching versus Circuit Switchingp. 212
Referencesp. 213
Real Chip Implementationp. 217
Introductionp. 217
BONE Seriesp. 217
BONE 1: Prototype of On-Chip Network (PROTON)p. 217
Overall Architecturep. 218
Packet Routing Schemep. 219
Off-Chip Connectivityp. 221
BONE 2: Low-Power Network on Chip and Network in Package (Slim Spider)p. 221
NoC Architecturep. 222
Low-Power Techniquesp. 224
Design Methodology and Chip Implementationp. 225
Networks in Package and Measurementp. 226
BONE 2 Chip Summaryp. 229
BONE 3 (Intelligent Interconnect System)p. 230
Supply-Voltage-Dependent Reference Voltagep. 231
Self-Calibrating Phase Differencep. 231
Adaptive-Link Bandwidth Controlp. 232
BONE 4 Flexible On-Chip Network (FONE)p. 232
NoC Evaluation Platformp. 232
NoC Run-Time Traffic-Monitoring Systemp. 233
Case Study: Portable Multimedia Systemp. 235
FONE Platform Summaryp. 239
BONE V1: Vision Application-1p. 239
Introductionp. 239
Architecture and Operationp. 239
Benefits of the MC-NoCp. 243
Evaluation of the MC-NoCp. 245
Industrial Implementationsp. 245
Intel's Tera-FLOP 80-Core NoCp. 245
Key Enablers for Tera-FLOP on a Chip [18]p. 246
NoC Architecture Overview [18]p. 246
Double-Pumped Crossbar Router and Mesochronous Interfacep. 248
Fine-Grained Power Managementp. 248
Intel's Scalable Communication Architecture [22]p. 249
Scalable Communication Corep. 249
Prototype Architecturep. 250
Control Plane (OCP-Bus)p. 252
Data Plane (NoC)p. 252
Data Flow and Reusabilityp. 253
Academic Implementationsp. 253
FAUST (Flexible Architecture of Unified System for Telecom)p. 253
RAWp. 256
Referencesp. 258
BONE Protocol Specificationp. 261
Overview of BONEp. 261
BONE Protocolp. 262
Packet Formatp. 262
BONE Signalsp. 264
Master Network Interface (MNI)p. 264
Up_Sampler (UPS)p. 267
Switch (SW)p. 268
Dn_Sampler (DNS)p. 269
Slave Network Interface (SNI)p. 270
Packet Transactionsp. 272
Timing Diagramsp. 275
Basic Read Packet Transactionp. 275
Basic Write Packet Transactionp. 278
UPS/DNS Timing Diagramp. 279
SW Timing Diagramp. 280
Indexp. 283
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