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Parag K. Lala, PhD, DSc(Eng), is the Cary and Lois Patterson Chair of Electrical Engineering at Texas A&M University-Texarkana. Dr. Lala is the author of five books, including Fault-Tolerant and Fault-Testable Hardware Design and Practical Digital Logic Design and Testing. Dr. Lala was named a Fellow of the IEEE for "contributions to the development of self-checking logic and associated checker design." He is also a Fellow of the Institution of Engineering and Technology, United Kingdom.
Preface | p. xiii |
Number Systems and Binary Codes | p. 1 |
Introduction | p. 1 |
Decimal Numbers | p. 1 |
Binary Numbers | p. 2 |
Basic Binary Arithmetic | p. 5 |
Octal Numbers | p. 8 |
Hexadecimal Numbers | p. 11 |
Signed Numbers | p. 13 |
Diminished Radix Complement | p. 14 |
Radix Complement | p. 16 |
Floating-Point Numbers | p. 19 |
Binary Encoding | p. 20 |
Weighted Codes | p. 20 |
Nonweighted Codes | p. 22 |
Exercises | p. 25 |
Fundamental Concepts of Digital Logic | p. 29 |
Introduction | p. 29 |
Sets | p. 29 |
Relations | p. 32 |
Partitions | p. 34 |
Graphs | p. 35 |
Boolean Algebra | p. 37 |
Boolean Functions | p. 41 |
Derivation and Classification of Boolean Functions | p. 43 |
Canonical Forms of Boolean Functions | p. 45 |
Logic Gates | p. 48 |
Exercises | p. 53 |
Combinational Logic Design | p. 59 |
Introduction | p. 59 |
Minimization of Boolean Expressions | p. 60 |
Karnaugh Maps | p. 63 |
Don't Care Conditions | p. 68 |
The Complementary Approach | p. 70 |
Quine-McCluskey Method | p. 73 |
Simplification of Boolean Function with Don't Cares | p. 78 |
Cubical Representation of Boolean Functions | p. 79 |
Tautology | p. 82 |
Complementation Using Shannon's Expansion | p. 84 |
Heuristic Minimization of Logic Circuits | p. 85 |
Expand | p. 85 |
Reduce | p. 88 |
Irredundant | p. 90 |
Espresso | p. 92 |
Minimization of Multiple-Output Functions | p. 95 |
NAND-NAND and NOR-NOR Logic | p. 98 |
NAND-NAND Logic | p. 98 |
NOR-NOR Logic | p. 101 |
Multilevel Logic Design | p. 102 |
Algebraic and Boolean Division | p. 105 |
Kernels | p. 106 |
Minimization of Multilevel Circuits Using Don't Cares | p. 109 |
Satisfiability Don't Cares | p. 110 |
Observability Don't Cares | p. 112 |
Combinational Logic Implementation Using EX-OR and AND Gates | p. 114 |
Logic Circuit Design Using Multiplexers and Decoders | p. 117 |
Multiplexers | p. 117 |
Demultiplexers and Decoders | p. 123 |
Arithmetic Circuits | p. 125 |
Half-Adders | p. 125 |
Full Adders | p. 126 |
Carry-Lookahead Adders | p. 129 |
Carry-Select Adder | p. 130 |
Carry-Save Addition | p. 130 |
BCD Adders | p. 132 |
Half-Subtractors | p. 133 |
Full Subtractors | p. 135 |
Two's Complement Subtractors | p. 135 |
BCD Substractors | p. 137 |
Multiplication | p. 138 |
Comparator | p. 140 |
Combinational Circuit Design Using PLDs | p. 141 |
PROM | p. 142 |
PLA | p. 144 |
PAL | p. 146 |
Exercises | p. 150 |
References | p. 155 |
Fundamentals of Synchronous Sequential Circuits | p. 157 |
Introduction | p. 157 |
Synchronous and Asynchronous Operation | p. 158 |
Latches | p. 159 |
Flip-Flops | p. 162 |
D Flip-Flop | p. 163 |
JK Flip-Flop | p. 165 |
T Flip-Flop | p. 167 |
Timing in Synchronous Sequential Circuits | p. 168 |
State Tables and State Diagrams | p. 170 |
Mealy and Moore Models | p. 172 |
Analysis of Synchronous Sequential Circuits | p. 175 |
Exercises | p. 177 |
References | p. 180 |
VHDL in Digital Design | p. 181 |
Introduction | p. 181 |
Entity and Architecture | p. 182 |
Entity | p. 182 |
Architecture | p. 184 |
Lexical Elements in VHDL | p. 185 |
Data Types | p. 187 |
Operators | p. 189 |
Concurrent and Sequential Statements | p. 192 |
Architecture Description | p. 194 |
Structural Description | p. 196 |
Behavioral Description | p. 199 |
RTL Description | p. 200 |
Exercises | p. 202 |
Combinational Logic Design Using VHDL | p. 205 |
Introduction | p. 205 |
Concurrent Assignment Statements | p. 206 |
Direct Signal Assignment | p. 206 |
Conditional Signal Assignment | p. 207 |
Selected Conditional Signal Assignment | p. 211 |
Sequential Assignment Statements | p. 214 |
Process | p. 214 |
If-Then Statement | p. 216 |
Case Statement | p. 220 |
If Versus Case Statements | p. 223 |
Loops | p. 225 |
For Loop | p. 225 |
While Loop | p. 229 |
For-Generate statement | p. 230 |
Exercises | p. 233 |
Synchronous Sequential Circuit Design | p. 235 |
Introduction | p. 235 |
Problem Specification | p. 236 |
State Minimization | p. 239 |
Partitioning Approach | p. 239 |
Implication Table | p. 242 |
Minimization of Incompletely Specified Sequential Circuits | p. 244 |
Derivation of Flip-Flop Next State Expressions | p. 249 |
State Assignment | p. 257 |
State Assignment Based on Decomposition | p. 261 |
Fan-out and Fan-in Oriented State Assignment Techniques | p. 265 |
State Assignment Based on 1-Hot Code | p. 271 |
State Assignment Using m-out-of-n Code | p. 271 |
Sequential PAL Devices | p. 273 |
Exercises | p. 286 |
References | p. 290 |
Counter Design | p. 291 |
Introduction | p. 291 |
Ripple (Asynchronous) Counters | p. 291 |
Asynchronous Up-Down Counters | p. 294 |
Synchronous Counters | p. 295 |
Gray Code Counters | p. 300 |
Shift Register Counters | p. 302 |
Ring Counters | p. 307 |
Johnson Counters | p. 310 |
Exercises | p. 313 |
References | p. 313 |
Sequential Circuit Design Using VHDL | p. 315 |
Introduction | p. 315 |
D Latch | p. 315 |
Flip-Flops and Registers | p. 316 |
D Flip-Flop | p. 316 |
T and JK Flip-Flops | p. 318 |
Synchronous and Asynchronous Reset | p. 320 |
Synchronous and Asynchronous Preset | p. 322 |
Registers | p. 322 |
Shift Registers | p. 324 |
Bidirectional Shift Register | p. 326 |
Universal Shift Register | p. 327 |
Barrel Shifter | p. 327 |
Linear Feedback Shift Registers | p. 329 |
Counters | p. 332 |
Decade Counter | p. 334 |
Gray Code Counter | p. 335 |
Ring Counter | p. 336 |
Johnson Counter | p. 337 |
State Machines | p. 338 |
Moore-Type State Machines | p. 338 |
Mealy-Type State Machines | p. 341 |
VHDL Codes for State Machines Using Enumerated Types | p. 342 |
Mealy Machine in VHDL | p. 345 |
User-Defined State Encoding | p. 351 |
1-Hot Encoding | p. 355 |
Case Studies | p. 356 |
Exercises | p. 368 |
References | p. 371 |
Asynchronous Sequential Circuits | p. 373 |
Introduction | p. 373 |
Flow Table | p. 374 |
Reduction of Primitive How Tables | p. 377 |
State Assignment | p. 379 |
Races and Cycles | p. 379 |
Critical Race-Free State Assignment | p. 381 |
Excitation and Output Functions | p. 387 |
Hazards | p. 390 |
Function Hazards | p. 391 |
Logic Hazards | p. 393 |
Essential Hazards | p. 396 |
Exercises | p. 398 |
References | p. 401 |
CMOS Logic | p. 403 |
Transmission Gates | p. 405 |
Clocked CMOS Circuits | p. 407 |
CMOS Domino Logic | p. 408 |
Index | p. 411 |
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