Rapid Prototyping of Digital Systems: Sopc Edition

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  • Edition: CD
  • Format: Paperback
  • Copyright: 2008-01-30
  • Publisher: Springer Verlag
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This book provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and excercises are also appropriate for an upper level course in digital logic or embedded systems. The goal of this text is to introduce fully integrated modern CAD tools, logic simulation, logic synthesis using hardware description languages, design hierarchy, current generation field programmable gate array (FPGA) technology, and SOPC design in the laboratory portion of the course. Even student laboratory projects can now implement entire digital and computer systems with hundreds of thousands of gates. The book includes a number of interesting and challenging laboratory projects involving serial communications, state machines with video output, video games and graphics, simple computers, keyboard and mouse interfaces, robotics, pipelined RISC processor cores, designing a computer system using a commercial processor core, C programs running on processor cores, and porting Linux to the board. Source files and additional example files are available on the CD-ROM for all designs presented in the text. The student version of the PC based CAD tool on the CD-ROM can be freely distributed to students.

Table of Contents

Tutorial I: The 15 Minute Designp. 2
Design Entry using the Graphic Editorp. 9
Compiling the Designp. 16
Simulation of the Designp. 17
Testing Your Design on an FPGA Boardp. 18
Downloading Your Design to the DE1 Boardp. 19
Downloading Your Design to the DE2 Boardp. 22
Downloading Your Design to the UP3 Boardp. 25
Downloading Your Design to the UP2 or UP1 Boardp. 27
The 10 Minute VHDL Entry Tutorialp. 29
Compiling the VHDL Designp. 32
The 10 Minute Verilog Entry Tutorialp. 34
Compiling the Verilog Designp. 36
Timing Analysisp. 38
The Floorplan Editorp. 39
Symbols and Hierarchyp. 40
Functional Simulationp. 41
Laboratory Exercisesp. 42
p. 46
FPGA and External Hardware Featuresp. 47
The FPGA Board's Memory Featuresp. 48
The FPGA Board's I/O Featuresp. 49
Obtaining an FPGA Development Board and Cablesp. 53
Programmable Logic Technologyp. 56
CPLDs and FPGAsp. 59
Altera MAX 7000S Architecture - A Product Term CPLD Devicep. 60
Altera Cyclone Architecture - A Look-Up Table FPGA Devicep. 62
Xilinx 4000 Architecture - A Look-Up Table FPGA Devicep. 65
Computer Aided Design Tools for Programmable Logicp. 67
Next Generation FPGA CAD toolsp. 68
Applications of FPGAsp. 69
Features of New Generation FPGAsp. 69
For additional informationp. 70
Laboratory Exercisesp. 71
Tutorial II: Sequential Design and Hierarchyp. 74
Install the Tutorial Files and FPGAcore Library for your boardp. 74
Open the tutor2 Schematicp. 75
Browse the Hierarchyp. 76
Using Buses in a Schematicp. 78
Testing the Pushbutton Counter and Displaysp. 79
Testing the Initial Design on the Boardp. 80
Fixing the Switch Contact Bounce Problemp. 81
Testing the Modified Design on the FPGA Boardp. 82
Laboratory Exercisesp. 83
FPGAcore Library Functionsp. 88
FPGAcore LCD_Display: LCD Panel Character Displayp. 90
FPGAcore DEC_7SEG: Hex to Seven-segment Decoderp. 92
FPGAcore Debounce: Pushbutton Debouncep. 94
FPGAcore OnePulse: Pushbutton Single Pulsep. 95
FPGAcore Clk_Div: Clock Dividerp. 96
FPGAcore VGA_Sync: VGA Video Sync Generationp. 97
FPGAcore Char_ROM: Character Generation ROMp. 99
FPGAcore Keyboard: Read Keyboard Scan Codep. 100
FPGAcore Mouse: Mouse Cursorp. 102
For additional informationp. 103
Using VHDL for Synthesis of Digital Hardwarep. 106
VHDL Data Typesp. 106
VHDL Operatorsp. 107
VHDL Based Synthesis of Digital Hardwarep. 108
VHDL Synthesis Models of Gate Networksp. 108
VHDL Synthesis Model of a Seven-segment LED Decoderp. 109
VHDL Synthesis Model of a Multiplexerp. 111
VHDL Synthesis Model of Tri-State Outputp. 112
VHDL Synthesis Models of Flip-flops and Registersp. 112
Accidental Synthesis of Inferred Latchesp. 114
VHDL Synthesis Model of a Counterp. 114
VHDL Synthesis Model of a State Machinep. 115
VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifterp. 117
VHDL Synthesis of Multiply and Divide Hardwarep. 118
VHDL Synthesis Models for Memoryp. 119
Hierarchy in VHDL Synthesis Modelsp. 123
Using a Testbench for Verificationp. 125
For additional informationp. 126
Laboratory Exercisesp. 126
Using Verilog for Synthesis of Digital Hardwarep. 130
Verilog Data Typesp. 130
Verilog Based Synthesis of Digital Hardwarep. 130
Verilog Operatorsp. 131
Verilog Synthesis Models of Gate Networksp. 132
Verilog Synthesis Model of a Seven-segment LED Decoderp. 132
Verilog Synthesis Model of a Multiplexerp. 133
Verilog Synthesis Model of Tri-State Outputp. 134
Verilog Synthesis Models of Flip-flops and Registersp. 135
Accidental Synthesis of Inferred Latchesp. 136
Verilog Synthesis Model of a Counterp. 136
Verilog Synthesis Model of a State Machinep. 137
Verilog Synthesis Model of an ALU with an Adder/Subtractor and a Shifterp. 138
Verilog Synthesis of Multiply and Divide Hardwarep. 139
Verilog Synthesis Models for Memoryp. 140
Hierarchy in Verilog Synthesis Modelsp. 143
For additional informationp. 144
Laboratory Exercisesp. 144
State Machine Design: The Electric Train Controllerp. 148
The Train Control Problemp. 148
Train Direction Outputs (DA1-DA0, and DB1-DB0)p. 149
Switch Direction Outputs (SW1, SW2, and SW3)p. 150
Train Sensor Input Signals (S1, S2, S3, S4, and S5)p. 150
An Example Controller Designp. 151
VHDL Based Example Controller Designp. 154
Verilog Based Example Controller Designp. 157
Automatically Generating a State Diagram of a Designp. 160
Simulation Vector file for State Machine Simulationp. 161
Running the Train Control Simulationp. 162
Running the Video Train System (After Successful Simulation)p. 162
A Hardware Implementation of the Train System Layoutp. 164
Laboratory Exercisesp. 166
A Simple Computer Design: The ¿P 3p. 170
Computer Programs and Instructionsp. 171
The Processor Fetch, Decode and Execute Cyclep. 172
VHDL Model of the ¿P 3p. 179
Verilog Model of the ¿P 3p. 182
Automatically Generating a State Diagram of the ¿P3p. 186
Simulation of the ¿P3 Computerp. 187
Laboratory Exercisesp. 188
p. 192
Video Display Technologyp. 192
Video Refreshp. 192
Using an FPGA for VGA Video Signal Generationp. 195
A VHDL Sync Generation Example: FPGAcore VGA_SYNCp. 196
Final Output Register for Video Signalsp. 198
Required Pin Assignments for Video Outputp. 198
Video Examplesp. 199
A Character Based Video Designp. 200
Character Selection and Fontsp. 200
VHDL Character Display Design Examplesp. 203
A Graphics Memory Design Examplep. 206
Video Data Compressionp. 207
Video Color Mixing using Ditheringp. 207
VHDL Graphics Display Design Examplep. 208
Higher Video Resolution and Faster Refresh Ratesp. 209
Laboratory Exercisesp. 210
Interfacing to the PS/2 Keyboard and Mousep. 214
PS/2 Port Connectionsp. 214
Keyboard Scan Codesp. 215
Make and Break Codesp. 215
The PS/2 Serial Data Transmission Protocolp. 216
Scan Code Set 2 for the PS/2 Keyboardp. 218
The Keyboard FPGAcorep. 220
A Design Example Using the Keyboard FPGAcorep. 223
Interfacing to the PS/2 Mousep. 224
The Mouse FPGAcorep. 226
Mouse Initializationp. 226
Mouse Data Packet Processingp. 227
An Example Design Using the Mouse FPGAcorep. 228
For Additional Informationp. 229
Laboratory Exercisesp. 229
Legacy Digital I/O Interfacing Standardsp. 232
Parallel I/O Interfacep. 232
RS-232C Serial I/O Interfacep. 233
SPI Bus Interfacep. 235
I2C Bus Interfacep. 237
For Additional Informationp. 239
Laboratory Exercisesp. 239
FPGA Robotics Projectsp. 242
The FPGA-bot Designp. 242
FPGA-bot Servo Drive Motorsp. 242
Modifying the Servos to make Drive Motorsp. 243
VHDL Servo Driver Code for the FPGA-botp. 244
Low-cost Sensors for an FPGA Robot Projectp. 246
Assembly of the FPGA-bot Bodyp. 259
I/O Connections to the board's Expansion Headersp. 266
Robot Projects Based on R/C Toys, Models, and Robot Kitsp. 267
For Additional Informationp. 275
Laboratory Exercisesp. 277
p. 284
The MIPS Instruction Set and Processorp. 284
Using VHDL to Synthesize the MIPS Processor Corep. 287
The Top-Level Modulep. 288
The Control Unitp. 291
The Instruction Fetch Stagep. 293
The Decode Stagep. 296
The Execute Stagep. 298
The Data Memory Stagep. 300
Simulation of the MIPS Designp. 301
MIPS Hardware Implementation on the FPGA Boardp. 302
For Additional Informationp. 303
Laboratory Exercisesp. 304
Introducing System-on-a-Programmable-Chipp. 310
Processor Coresp. 310
SOPC Design Flowp. 311
Initializing Memoryp. 313
SOPC Design versus Traditional Design Modalitiesp. 315
An Example SOPC Designp. 316
Hardware/Software Design Alternativesp. 317
For additional informationp. 317
Laboratory Exercisesp. 318
Tutorial III: Nios II Processor Software Developmentp. 322
Install the DE board filesp. 322
Starting a Nios II Software Projectp. 322
The Nios II IDE Softwarep. 324
Generating the Nios II System Libraryp. 325
Software Design with Nios II Peripheralsp. 326
Starting Software Design - main()p. 329
Downloading the Nios II Hardware and Software Projectsp. 330
Executing the Softwarep. 331
Starting Software Design for a Peripheral Test Programp. 331
Handling Interruptsp. 334
Accessing Parallel I/O Peripheralsp. 335
Communicating with the LCD Display (DE2 only)p. 336
Testing SRAMp. 339
Testing Flash Memoryp. 340
Testing SDRAMp. 341
Downloading the Nios II Hardware and Software Projectsp. 346
Executing the Softwarep. 347
For additional informationp. 347
Laboratory Exercisesp. 348
Tutorial IV: Nios II Processor Hardware Designp. 352
Install the DE board filesp. 352
Creating a New Projectp. 352
Starting SOPC Builderp. 353
Adding a Nios II Processorp. 355
Adding UART Peripheralsp. 358
Adding an Interval Timer Peripheralp. 359
Adding Parallel I/O Componentsp. 360
Adding an SRAM Memory Controllerp. 361
Adding an SDRAM Memory Controllerp. 362
Adding the LCD Module (DE2 Board Only)p. 362
Adding an External Busp. 363
Adding Components to the External Busp. 364
Global Processor Settingsp. 364
Finalizing the Nios II Processorp. 365
Add the Processor Symbol to the Top-Level Schematicp. 366
Create a Phase-Locked Loop Componentp. 367
Complete the Top-Level Schematicp. 368
Design Compilationp. 368
Testing the Nios II Projectp. 369
For additional informationp. 370
Laboratory Exercisesp. 370
Operating System Support for SOPC Designp. 374
Nios II OS Supportp. 376
eCosp. 377
¿C/OS-IIp. 378
¿Clinuxp. 379
Implementing the ¿Clinux on the DE Boardp. 380
Hardware Design for ¿Clinux Supportp. 380
Configuring the DE Boardp. 382
Exploring ¿Clinux on the DE Boardp. 385
PS/2 Device Support in ¿Clinuxp. 386
Video Display in ¿Clinuxp. 386
USB Devices in ¿Clinux (DE2 Board Only)p. 387
Network Communication in ¿Clinux (DE2 Board Only)p. 387
For additional informationp. 388
Laboratory Exercisesp. 388
Generation of Pseudo Random Binary Sequencesp. 391
Quartus II Design and Data File Extensionsp. 393
Common FPGA Pin Assignmentsp. 394
ASCII Character Codep. 396
Common I/O Connector Pin Assignmentsp. 397
Glossaryp. 399
Indexp. 407
About the Accompanying DVDp. 411
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