The Simple Art of SoC Design

by Keating, Michael

• ISBN13: 9781441985859
• ISBN10: 1441985859
• Format: Hardcover
• Copyright: 2011-05-31
• Publisher: Springer Verlag

Summary

This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques for measuring and minimizing complexity in RTL code. Finally, it discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages must progress to address the needs of tomorrow#xE2;#xAC;"s SoC designs.

Table of Contents

The Third Revolution	p. 1
The Problem	p. 1
Divide and Conquer	p. 3
The General Model	p. 4
Rule of Seven	p. 6
Tightly Coupled vs. Loosely Coupled Systems	p. 7
The Challenge of Verification	p. 10
The Pursuit of Simplicity	p. 11
The Changing Landscape of Design	p. 12
Structure of This Book	p. 12
Simplifying RTL Design	p. 15
Challenges	p. 15
Syntactic Fluff	p. 16
Concurrency and State Space	p. 17
Techniques	p. 19
Encapsulating Combinational Code	p. 20
Structuring Sequential Code	p. 21
Using High Level Data Types	p. 23
Thinking High-level	p. 25
Reducing Complexity in Control-Dominated Designs	p. 27
Original Code	p. 28
State Space in the Original Design	p. 29
Partitioning	p. 30
Comments	p. 30
Syntactic fluff	p. 32
Preprocessing Sequential Code	p. 32
Preprocessing Combinational Code	p. 34
Refactoring Sequential Code	p. 35
Recodingthe State Machine	p. 35
Relocating Other Sequential Code	p. 37
Rewriting Combinational Code	p. 38
Analyzing the New Code	p. 40
Restructuring for a Hierarchical State Machine	p. 41
System Verilog	p. 41
Simplified Block Diagram	p. 43
Summary	p. 44
Hierarchical State Machines	p. 47
Restructuring for a Hierarchical State Machine	p. 47
General Model for HFSMs	p. 47
Converting the BCU to a HFSM	p. 51
Measuring and Minimizing State Space	p. 55
Input, Output, and Internal State Space	p. 55
Preliminary Calculations of State Space	p. 56
Shallow vs. Deep State Space	p. 58
The Cross Product of State Spaces	p. 60
Sequential Processes and Internal State	p. 63
Encapsulating Sequential Code	p. 63
State Machines as Sequential Processes	p. 64
Hierarchical State Machines	p. 64
Examples	p. 65
Summary- Counting State	p. 68
Input State Space	p. 68
Output State Space	p. 68
Internal State Space	p. 68
State Space for Hierarchical State Machines	p. 69
Verification	p. 71
Some Simple Examples of Verifiable Designs	p. 72
Verification overview	p. 73
Goals of Complete Verification	p. 74
Verifying State Machines	p. 75
Example: The Bcu	p. 77
A Canonical Design	p. 80
Structure of the Canonical Design	p. 80
Separating Data from Control	p. 81
Verifying the Control Path: The State Machine	p. 82
Line Coverage	p. 83
Condition Coverage	p. 83
Conditional Range Coverage	p. 83
Cycle Coverage	p. 84
Input State Coverage	p. 84
Verifying the Data Path	p. 85
Data Path Uniqueness	p. 85
Data Range Coverage	p. 85
Verifying the Data Path Algorithm	p. 86
Summary	p. 86
Reducing Complexity in Data Path Dominated Designs	p. 89
Problems and Limitations in the Original Code	p. 91
Minimizing Lines of Code	p. 92
Other Versions of the Code	p. 96
Task Version	p. 97
More Code Size Reduction	p. 98
Untimed Version	p. 100
Experimental Versions	p. 102
Simulation Results for the Different Versions of the Dct	p. 103
Reference Versions	p. 103
Synthesis Results	p. 105
Gates per Line of Code	p. 105
Formal Verification	p. 106
Canonical Design	p. 106
Summary	p. 107
Simplifying Interfaces	p. 109
Command-based Interface	p. 109
Example: CPU Pipeline	p. 111
Example: Bcu	p. 113
Example: Usb	p. 115
Impact on Verification	p. 117
Separating Data and Control	p. 117
General Connectivity	p. 118
Concurrency and Analysis	p. 120
Total State Space	p. 120
Summary	p. 120
Complexity at the Chip Level	p. 123
From Command to Transaction Interfaces	p. 126
Jpeg Example	p. 127
Usb Example	p. 128
Software Driver	p. 128
Virtual Platforms and Software Development	p. 129
Connectivity and Complexity at the SoC Level	p. 129
Function and Structure	p. 130
Connectivity and Bandwidth	p. 130
Transactions and Complexity	p. 131
Limits to Chip Level Verification	p. 133
Sub-systems and SoC Design	p. 134
Summary	p. 137
Raising Abstraction Above Rtl	p. 139
The Challenge	p. 139
Current High Level Synthesis Tools	p. 140
Closing the Abstraction Gap	p. 145
SystemC	p. 146
The Right Usage Model for High Level Design	p. 146
SystemVerilog as a High Level Design Language	p. 147
Raising the Level of Abstraction of Rtl	p. 149
Domain Specific Languages	p. 150
SystemVerilog as a Domain Specific Language	p. 150
SystemVerilog Primitives	p. 151
Proposal	p. 152
SystemVerilog Extensions	p. 155
Overview	p. 155
Basic Extensions	p. 155
smodule	p. 158
bit_ff	p. 159
bit_comb	p. 159
$clock	p. 159
$reset	p. 159
state_machine	p. 160
state_var	p. 160
done (to signal the end of a sub-state machine activity)	p. 160
combinational and sequential assignments in the same case statement	p. 160
Other Capabilities	p. 161
First	p. 161
Functions and Tasks	p. 161
Assignments Outside State Machines	p. 161
Iterative State Loops	p. 162
Fork and Join	p. 168
Summary	p. 168
There is No Substitute for Good Code	p. 169
The Future of Design	p. 171
Design	p. 172
Function Does Not Scale	p. 172
Small is Beautiful - and Tractable	p. 175
How Does IP Help?	p. 175
Automation and Scaling	p. 176
The Future of Design	p. 177
Verification	p. 177
Visualization	p. 178
Drivers of the Solution	p. 179
Summary	p. 180
Appendix A	p. 181
Appendix B	p. 191
Appendix C	p. 207
Appendix D	p. 223
References	p. 231
Index	p. 233
Table of Contents provided by Ingram. All Rights Reserved.