SOI Circuit Design Concepts

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  • Format: Paperback
  • Copyright: 2007-11-01
  • Publisher: Springer Verlag

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Supplemental Materials

What is included with this book?


Market demand for microprocessor performance has motivated continued scaling of CMOS through a succession of lithography generations. Quantum mechanical limitations to continued scaling are becoming readily apparent. Partially Depleted Silicon-on-Insulator (PD-SOI) technology is emerging as a promising means of addressing these limitations. It also introduces additional design complexity which must be well understood. SOI Circuit Design Concepts first introduces the student or practising engineer to SOI device physics and its fundamental idiosyncrasies. It then walks the reader through realizations of these mechanisms which are observed in common high-speed microprocessor designs. Rules of thumb and comparisons to conventional bulk CMOS are offered to guide implementation. SOI's ultimate advantage, however, may lie in the unique circuit topologies it supports; a number of these novel new approaches is also described. SOI Circuit Design Concepts draws upon the latest industry literature as well as the firsthand experiences of its authors. It is an ideal introduction to the concepts of governing SOI use and provides a firm foundation for further study of this exciting new technology paradigm.

Table of Contents

The Time for SOIp. 1
Technology Scaling in VLSIp. 1
The End of Moore's Law?p. 1
The Case for PD-SOIp. 1
SOI Device Structuresp. 2
Introductionp. 2
Wafer Fabricationp. 2
Patterning SOI Regionsp. 2
Transistor Structuresp. 2
Diodesp. 2
Resistorsp. 2
Decoupling Capacitorsp. 2
SOI Device Electrical Propertiesp. 3
Introductionp. 3
SOI MOSFET's Junction Diodep. 3
Impact Ionizationp. 3
Floating Body Effectsp. 3
SOI MOSFET Modelingp. 3
Insulator-Related Effectsp. 3
Composite Responsesp. 3
Static Circuit Design Responsep. 4
Introductionp. 4
Parameters of Interest to Circuit Designersp. 4
First Switch vs. Second Switchp. 4
First Switch vs. Steady Statep. 4
Static Circuit Response to SOIp. 4
Passgate Circuit Responsep. 4
Dynamic Circuit Design Considerationsp. 5
Introductionp. 5
Dynamic Circuit Responsep. 5
Preferred Dynamic Design Practicesp. 5
Keeping Dynamic SOI Problems in Perspectivep. 5
Soft Errors in Dynamic Logicp. 5
Dynamic Logic Performancep. 5
SRAM Cache Design Considerationsp. 6
Overviewp. 6
Writing a Cellp. 6
Reading a Cellp. 6
Cell Stability and Cell Biasp. 6
SRAM Noise Considerationsp. 6
Precharging Circuitryp. 6
Soft Error Upsetsp. 6
Array Test in PD-SOIp. 6
p. Specialized
Introductionp. 7
Timing Elementsp. 7
Latch Response in SOIp. 7
Input/Output Circuitryp. 7
Electro-Static Discharge (ESD) Protectionp. 7
Global Chip Design Considerationsp. 8
Introductionp. 8
Temperature Effectsp. 8
Noise Immunityp. 8
Power Consumptionp. 8
Power Supply Issues Noisep. 8
System Performancep. 8
SOI Timing Variabilityp. 8
Future Opportunities in SOIp. 9
Introductionp. 9
Floating body Effect Suppressionp. 9
3-Dimensional SOIp. 9
Future Scaling Opportunitiesp. 9
About the Authors
Table of Contents provided by Publisher. All Rights Reserved.

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