9780792377627

Soi Circuit Design Concepts

by ;
  • ISBN13:

    9780792377627

  • ISBN10:

    0792377621

  • Format: Hardcover
  • Copyright: 2000-01-01
  • Publisher: Kluwer Academic Pub

Note: Supplemental materials are not guaranteed with Rental or Used book purchases.

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Supplemental Materials

What is included with this book?

Summary

Market demand for microprocessor performance has motivated continued scaling of CMOS through a succession of lithography generations. Quantum mechanical limitations to continued scaling are becoming readily apparent. Partially Depleted Silicon-on-Insulator (PD-SOI) technology is emerging as a promising means of addressing these limitations. It also introduces additional design complexity which must be well understood. SOI Circuit Design Concepts first introduces the student or practising engineer to SOI device physics and its fundamental idiosyncrasies. It then walks the reader through realizations of these mechanisms which are observed in common high-speed microprocessor designs. Rules of thumb and comparisons to conventional bulk CMOS are offered to guide implementation. SOI's ultimate advantage, however, may lie in the unique circuit topologies it supports; a number of these novel new approaches is also described. SOI Circuit Design Concepts draws upon the latest industry literature as well as the firsthand experiences of its authors. It is an ideal introduction to the concepts of governing SOI use and provides a firm foundation for further study of this exciting new technology paradigm.

Author Biography

Kerry Bernstein is a senior technical staff member and lead technologist in the Microprocessor Development Group at IBM Microelectronic Division's Essex Junction, Vermont facility.

Table of Contents

Preface xv
The Time for SOI
1(12)
Technology Scaling in VLSI
1(1)
The End of Moore's Law?
2(4)
The Case for PD-SOI
6(3)
Why Partially Depleted SOI?
6(1)
Why SOI Now?
7(2)
Summary
9(4)
SOI Device Structures
13(16)
Introduction
13(1)
Wafer Fabrication
14(3)
SIMOX
14(2)
Bonded SOI Wafers
16(1)
Smart Cut
17(1)
Patterning SOI regions
17(1)
Transistor Structures
18(6)
Partially Depleted FET Structures
19(3)
Body Contacts
22(2)
Diodes
24(1)
Poly Bounded or Gated Diodes
24(1)
Resistors
25(1)
Decoupling Capacitors
26(1)
Summary
27(2)
SOI Device Electrical Properties
29(38)
Introduction
29(1)
SOI MOSFET's Junction Diode
30(2)
Impact Ionization
32(2)
Floating Body Effects
34(19)
History Effect and Threshold Voltage Variability
34(3)
The Body Potential Range
37(1)
The Body-Charging / Device Wearout Connection
37(4)
The ``Kinks''
41(2)
Elevated DIBL
43(1)
Reduced Body Effect / Source Follower Action
44(2)
Reduced Short Channel Effect
46(1)
Bipolar Device Action
47(4)
Lower Temperature Sensitivity
51(1)
Backchannel Device
52(1)
SOI MOSFET Modeling
53(1)
DC Discrete Element Representation
53(1)
AC Discrete Element Representation
54(1)
Insulator-Related Effects
54(6)
Self Heating
55(2)
Diffusion Capacitance Reduction
57(1)
Latch-Up Elimination
57(2)
SER Improvement
59(1)
Composite Responses
60(4)
Device Leakage - 5 Mechanisms
60(1)
Conservation of Charge
61(1)
Other Parasitic Active Elements
62(2)
Summary
64(3)
Static Circuit Design Response
67(28)
Introduction
67(1)
Parameters of Interest to Circuit Designers
67(2)
First Switch vs. Second Switch
69(6)
First Switch vs. Steady State
75(1)
Static Circuit Response to SOI
76(8)
Inverter Response
76(3)
Noise Response for Inverters
79(1)
NAND Gate Response
80(4)
Passgate Circuit Response
84(8)
Summary
92(3)
Dynamic Circuit Design Considerations
95(24)
Introduction
95(1)
Dynamic Circuit Response
96(6)
Dynamic History Effect
96(1)
Dynamic Charge Sharing
97(2)
Miller Capacitance
99(2)
Half-Latch / Keeper Device Sizing
101(1)
Preferred Dynamic Design Practices
102(8)
Predischarging
103(2)
Cross-coupling of Dynamic Inputs
105(1)
Reordered Inputs
105(2)
Early Setup
107(1)
Logic Remapping
107(1)
Complex Domino
108(1)
Dynamic Noise Suppression
108(2)
Keeping Dynamic SOI Problems in Perspective
110(3)
Bipolar Effects and Noise in the 2W AND-OR
111(1)
Charge Sharing Effects and Noise in the 2W AND-OR
112(1)
Soft Errors in Dynamic Logic
113(2)
Dynamic Logic Performance
115(1)
Conclusions
116(3)
SRAM Cache Design Considerations
119(30)
Overview
119(1)
Writing a Cell
120(3)
Capacitive Discharge Current
121(1)
CMOS Subthreshold Leakage
122(1)
Diode and Bipolar Currents
123(1)
Reading a Cell
123(8)
Read Leakage
124(1)
Sense Amplifier Bias
124(4)
Read Sense-Amp Strobe Timing vs. Read Frequency
128(1)
Single Polarity SRAMS
129(1)
Word Line History
130(1)
Cell Stability and Cell Bias
131(7)
Transfer Ratio
131(1)
Mistracking
132(1)
Self Heating
133(1)
Body Bias
133(2)
Supply Rail Droop
135(1)
Body-to-Body Coupling
135(1)
Defect-Induced Bias
135(1)
Passive History Effects
136(1)
Making Sense of All This Bias!
137(1)
SRAM Noise Considerations
138(2)
Precharging Circuitry
140(1)
Soft Error Upsets
141(4)
Array Test in PD-SOI
145(1)
Summary
146(3)
Specialized Function Circuits in SOI
149(16)
Introduction
149(1)
Timing Elements
149(4)
Latch Response in SOI
153(2)
Latch Stability and Noise
153(1)
Bipolar Charge Loss
154(1)
Clock Skew due to History Effect
155(1)
Input / Output Circuitry
155(3)
Clock Drivers
156(1)
Data Drivers
156(1)
Clock Receivers
157(1)
Data Receivers
158(1)
Voltage Reference
158(1)
Electro-Static Discharge (ESD) Protection
158(3)
Summary
161(4)
Global Chip Design Considerations
165(30)
Introduction
165(1)
Temperature Effects
166(9)
Design Considerations, Normal Operation
166(1)
Stress Considerations
167(2)
Low Temperature Operation
169(6)
Noise Immunity
175(3)
Crosstalk (Capacitive Coupling)
176(1)
Delay Noise
176(1)
Logic Noise
177(1)
Simultaneous Switching
178(1)
Power Consumption
178(7)
Power Supply Issues Noise
185(1)
System Performance
186(1)
SOI Timing Variability
187(4)
Total Delay Variation
188(1)
History Variation
189(1)
Body Initialization
190(1)
Summary
191(4)
Future Opportunities in SOI
195
Introduction
195
Floating Body Effect Suppression
196
Charge-Balanced Device Design
196
Field Shield Isolation
198
BESS
199
Body-Linked Device
200
Patterned Insulators
201
DTCMOS
203
DTCMOS Low Voltage Static Logic
203
0.5V Pass-Gate Logic
205
DTCMOS Elevated Voltage Schemes
206
DGCMOS
208
3-Dimensional SOI
209
Future Scaling Opportunities
210
Summary
212

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