About the ARM Architecture The ARM architecture is the industry's leading 16/32-bit embedded RISC processor solution. ARM Powered microprocessors are being routinely designed into a wider range of products than any other 32-bit processor. This wide applicability is made possible by the ARM architecture, resulting in optimal system solutions at the crossroads of high performance, low power consumption and low cost. About the book This is the authoritative reference guide to the ARM RISC architecture. Produced by the architects that are actively working on the ARM specification, the book contains detailed information about all versions of the ARM and Thumb instruction sets, the memory management and cache functions, as well as optimized code examples. 0201737191B05092001

Preface
About this manual	p. iv
Architecture versions and variants	p. v
Using this manual	p. x
Conventions	p. xii
CPU Architecture
Introduction to the ARM Architecture
About the ARM architecture	p. 2
ARM instruction set	p. 5
Programmer's Model
Data types	p. 2
Processor modes	p. 3
Registers	p. 4
General-purpose registers	p. 5
Program status registers	p. 9
Exceptions	p. 13
Memory and memory-mapped I/O	p. 22
The ARM Instruction Set
Instruction set encoding	p. 2
The condition field	p. 5
Branch instructions	p. 7
Data-processing instructions	p. 9
Multiply instructions	p. 12
Miscellaneous arithmetic instructions	p. 14
Status register access instructions	p. 15
Load and store instructions	p. 17
Load and Store Multiple instructions	p. 21
Semaphore instructions	p. 23
Exception-generating instructions	p. 24
Coprocessor instructions	p. 25
Extending the instruction set	p. 27
ARM Instructions
Alphabetical list of ARM instructions	p. 2
ARM instructions and architecture versions	p. 113
ARM Addressing Modes
Addressing Mode 1 - Data-processing operands	p. 2
Addressing Mode 2 - Load and Store Word or Unsigned Byte	p. 13
Addressing Mode 3 - Miscellaneous Loads and Stores	p. 34
Addressing Mode 4 - Load and Store Multiple	p. 48
Addressing Mode 5 - Load and Store Coprocessor	p. 56
The Thumb Instruction Set
About the Thumb instruction set	p. 2
Instruction set encoding	p. 4
Branch instructions	p. 6
Data-processing instructions	p. 8
Load and Store Register instructions	p. 15
Load and Store Multiple instructions	p. 18
Exception-generating instructions	p. 20
Undefined instruction space	p. 21
Thumb Instructions
Alphabetical list of Thumb instructions	p. 2
Thumb instructions and architecture versions	p. 104
The 26-bit Architectures
Overview of the 26-bit architectures	p. 2
Format of register 15	p. 4
26-bit PSR update instructions	p. 6
Address exceptions	p. 8
Backwards compatibility from 32-bit architectures	p. 9
ARM Code Sequences
Arithmetic instructions	p. 2
Branch instructions	p. 5
Load and Store instructions	p. 7
Load and Store Multiple instructions	p. 10
Semaphore instructions	p. 11
Other code examples	p. 12
Enhanced DSP Extension
About the enhanced DSP instructions	p. 2
Saturated integer arithmetic	p. 3
Saturated Q15 and Q31 arithmetic	p. 4
The Q flag	p. 5
Enhanced DSP instructions	p. 6
Alphabetical list of enhanced DSP instructions	p. 8
Memory and System Architectures
Introduction to Memory and System Architectures
About the memory system	p. 2
System-level issues	p. 4
The System Control Coprocessor
About the System Control coprocessor	p. 2
Registers	p. 3
Register 0: ID codes	p. 6
Register 1: Control register	p. 13
Registers 2-15	p. 17
Memory Management Unit
About the MMU architecture	p. 2
Memory access sequence	p. 4
Translation process	p. 6
Access permissions	p. 16
Domains	p. 17
Aborts	p. 18
CP15 registers	p. 23
Protection Unit
About the Protection Unit	p. 2
Overlapping regions	p. 5
CP15 registers	p. 6
Caches and Write Buffers
About caches and write buffers	p. 2
Cache organization	p. 3
Types of cache	p. 5
Cachability and bufferability	p. 8
Memory coherency	p. 10
CP15 registers	p. 14
Fast Context Switch Extension
About the FCSE	p. 2
Modified virtual addresses	p. 3
Enabling the FCSE	p. 5
CP15 registers	p. 6
Vector Floating-point Architecture
Introduction to the Vector Floating-point Architecture
About the Vector Floating-point architecture	p. 2
Overview of the VFP architecture	p. 3
Compliance with the IEEE 754 standard	p. 7
IEEE 754 implementation choices	p. 8
VFP Programmer's Model
Floating-point formats	p. 2
Rounding	p. 9
Floating-point exceptions	p. 10
Flush-to-zero mode	p. 13
Floating-point general-purpose registers	p. 14
System registers	p. 19
Reset behavior and initialization	p. 26
VFP Instruction Set Overview
Data-processing instructions	p. 2
Load and Store instructions	p. 13
Register transfer instructions	p. 17
VFP Instructions
Alphabetical list of VFP instructions	p. 2
VFP Addressing Modes
Addressing Mode 1 - Single-precision vectors (non-monadic)	p. 2
Addressing Mode 2 - Double-precision vectors (non-monadic)	p. 8
Addressing Mode 3 - Single-precision vectors (monadic)	p. 14
Addressing Mode 4 - Double-precision vectors (monadic)	p. 19
Addressing Mode 5 - VFP load/store multiple	p. 24
Glossary
Index
Table of Contents provided by Syndetics. All Rights Reserved.

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Arm Architecture Reference Manual

9780201737196

0201737191

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