Praise for Signal Integrity Effects in Custom IC and ASIC Designs

"For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits."
–Alina Deutsch, Research Staff Member
T.J. Watson Research Center, International Business Machines

"This book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip."
–Kenneth L. Shepard, Professor
Columbia University

"This book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity."
–Jake Buurma, Senior Vice President
Worldwide Research & Development, Cadence Design Systems, Inc.

"This collection of papers . . . is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection."
–Alberto Sangiovanni-Vincentelli, Professor
University of California Berkeley

"The editor has gathered together a collection of papers, both tutorial and advanced, that address a broad range of interconnect problems."
–Jacob White, Professor
Massachusetts Institute of Technology

Signal Integrity Effects in Custom IC and ASIC Designs compiles recent expert research papers in state-of-the-art IC (Integrated Circuits) design. It offers a detailed focus on all the major topics in understanding and modeling real-world IC signal integrity issues for CAD and IC design engineers, as well as graduate engineering students.

Practical, in-depth discussion of interconnect effects, inductance effects, power grid and distribution noise, and substrate noise and coupling is included. This specialized coverage provides the knowledge necessary to overcome serious problems in new, more complicated IC designs, such as: *Wired and wireless communications ICs *Large custom analog mixed-signal ICs *ASIC designs from 0.12 microns and above *Integrated custom IC blocks in ASIC (Applications-Specific Integrated Circuit) designs

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* ".offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity." --Jake Buurma, Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc.
* Covers signal integrity effects in high performance Radio Frequency (RF) IC
* Brings together research papers from the past few years that address the broad range of issues faced by IC designers and CAD managers now and in the future A Wiley-IEEE Press publication

Signal Integrity Effects in Custom IC and ASIC Designs

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John Wiley & Sons

ISBN: 0-471-15042-8

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Chapter One

Signal Integrity Effects in System-on-Chip Designs - A Designer's Perspective

LAURENCE H. COOKE (Independent Consultant), MARTIJN GOOSSENS (Philips Research, Netherlands), PAUL HOXEY (ARM, UK), TAKAHIDE INOUE (Japanese Special Interest Group, VSIA), DAVID OVERHAUSER (Simplex Solutions, USA), PRASHANT SAXENA (Intel Corp, USA), RAMINDERPAL SINGH (IBM, USA)

Abstract - In this paper, we present a designer's perspective to the signal integrity issues that affect authors and integrators of blocks used in System-on-Chip designs. In particular, after presenting typical process parameters used for such designs, we focus on signal integrity issues in the context of power grid noise, interconnect crosstalk and substrate coupling. In each case, we describe the problem from the point of view of System-on-Chip designers (both block authors and block integrators), and briefly discuss standard techniques that are used to alleviate the problem.

1 INTRODUCTION

System-on-Chip (SoC) design has taken many meanings for IC designers. However, for all of them, the issues of Intellectual Property (IP) block integration and verification are important problems. As technologies scale, it becomes very difficult to both design (or "author") IP blocks and then integrate them. In this paper, a background is presented on the Signal Integrity (SI) problems that designers face and the overall need to tackle them in SoC designs.

It is important for the designer to understand the design process of IP block authoring to integration, and the processes that System-on-Chip Designers typically design within. The following subsections cover these topics. These are followed by sections on the issues of power grid noise, interconnect crosstalk, and substrate coupling. This paper complements the material presented in this book, and although much of the content in this paper involves a basic understanding of SI, advanced knowledge is not a prerequisite.

1.1 The Process of System-on-Chip Design

Today's semiconductor fabrication technology can manufacture chips containing tens of millions of gates, thus allowing full systems to be integrated onto a single semiconductor chip. Using current Electronic Design Automation (EDA) techniques, creating such SoCs from scratch would require an army of engineers. As a result, there has been considerable effort on the development of methodologies centered on design reuse in order to minimize the amount of re-engineering of each new chip. Most of these SoC methodologies involve the selection and integration of appropriate existing internal or third party IP blocks - called Virtual Components (VCs) - based on an architecture which meets the original product requirement.

This SoC methodology effort involves the specification of standard formats and interface requirements that will ensure the successful reuse and integration of such VCs. This allows the separation of VC creation and SoC integration, and has helped legitimize the emerging third party IP business. As a result, most SoC design methodologies focus on the creation of IP libraries containing appropriately collared VCs, along with the techniques to extract and integrate these existing, qualified VCs into an SoC. By the very nature of these methods, there is considerable data hidden within the VCs. The key to successful integration is the provision of sufficient information about each VC to the integrator to allow successful integration of these components. If the components are all soft (i.e., in an RTL format such as VHDL or Verilog), such data hiding is minimized and the blocks may be physically implemented together. On the other hand, if the VCs are hard (i.e., polygons in a layout in, for example, GDSII format), a form of block-based implementation must be used. In this case, the VCs are viewed as black boxes that must be physically integrated together. Their functional, clock, test and physical requirements must be sufficiently delineated to properly integrate such VCs with the rest of the SoC design.

As a VC block author completes the design, there is a need to "package" the design so that it is useful to the integrator. In this packaging process, the design remains unchanged, but several data views are prepared for the design. It is these views that allow the integrator to understand and integrate the design into a larger system without requiring complete visibility into the design. As SI issues become increasingly important with process scaling, the SI view of the design is also becoming an important part of the VC design. This paper therefore focuses on the data transfer involved in the creation of this view, as well as on design issues in the integration of the VC block. Figure 1 shows some of the views required for successful integration of analog (and custom) VCs.

For a detailed background (excluding SI effects) to SoC design and verification, refer to [1] and [2].

1.2 Target Process

SoC designs tend to be a generation or two behind leading edge designs. To help provide some context for the process parameters within which such designs are created, Table 1 shows some data in terms of current and next generation process technologies, as well as its usage model for high-performance and cost-performance applications. Most of this data has been extracted from the 1999 version of the International Technology Roadmap for Semiconductors.

The table clearly shows why there is a growing SI problem as designs move toward 0.13 micron processes. More of the wire surface is in the side walls (with aspect ratios growing from 1.8 to 2.1) and the pitch is reducing (from 0.56 to 0.39 microns) while the switching frequencies are increasing (from 30 to 40 GHz) and chip size, which is related to wire length, grows (from 340 to 430 mm2). All of these factors aggravate the already significant crosstalk issues in 0.18 micron processes. Similarly, the reduction in voltage (from 1.8 to 1.5 Volts) coupled with the increase in power (from 90 to 130 Watts) is equivalent to a 73% increase in current (from 50 to 87 amps). This coupled with a faster clock (from 1.2 to 1.6 GHz) further stresses power distribution design. Similarly, the tripling of the logic density (from 6.2M to 18M tranistors/cm2) and memory (from 256M to 768M transistors/cm2), and their associated increases in charge and current densities, further aggravates substrate coupling issues. Thus, as shown by these comparisons, all the parameters which are thought to be improving the semiconductor processing also unfortunately worsen the SI issues.

1.3 Snapshot of SI Problems with Scaling Technologies

Table 2 shows a snapshot of the SI effects designers experience (or expect to experience) in various design types and technologies. For System-on-Chip design, these problems refer to the various IP blocks that are provided for integration. As is evident from this table, problems that are considered "esoteric" and applicable only to high-end custom designs such as microprocessors often move successively to Application Specific Integrated Circuit (ASIC) designs within a couple of process generations. Thus, one can safely predict that signal integrity issues that have been plaguing high-end microprocessor designers for several years now will also become a significant headache for ASIC and SoC designers in the near future. Figure 2 shows a snapshot of interconnect performance parameters as technologies scale. This data helps show the relative importance of the delay of the interconnect compared to the gate delay, using Aluminum and Copper metal routing with SiO2 and Low-K dielectrics.

2 POWER GRID

The trend of increasing design size and power consumption and decreasing supply voltage (thus increasing current) is resulting in an increase in the amount of power grid IR drop and ground bounce on chips. This trend is critical as the IR drop and ground bounce noise margins are decreasing along with the supply voltage. Chip failures due to power grid issues, whether IR drop or electromigration, are already being discovered by chip designers. Since these issues are related to the number and way components are assembled on a chip and are primarily a global phenomenon, power grid analysis is becoming a required addition to many design flows. Of course, not all designs require power grid analysis, but increasing numbers are susceptible to problems.

In many designs the approach is to overdesign the power grid of the chip at the cost of metal consumption, which would otherwise be used for signal routing. The challenge facing designers is in determining how much of a power grid is actually overdesign, especially if there is no testing of the grid. As the use of more and larger components increases, this challenge becomes greater. In fact, even overdesigned grids can experience problems if the logic under the grid is not sufficiently connected to the grid (for example, due to insufficient vias from the global grid to component pins).

When components of a design do not see the specified power rail voltage, functional or timing failures will result. Functional failures result from insufficient power for the component to operate properly. Timing failures result from gate delays increasing beyond the timing requirements of the paths (and ultimately cause setup or hold failures). These failures can be intermittent if the power voltage assumption is violated only under certain operating conditions. Electromigration failures could even result in the failure of the chip at a customer site. Because power grid issues are due to interactions between components and the global integration of components, a set of interface specifications are necessary to permit the verification of the power grid by the chip integrator.

Another signal integrity issue that will soon become significant while designing power grids is that of providing adequate current return paths to counter inductive coupling. Note that the operating frequency for the purposes of inductance analysis is decided by the signal rise time and not the clock period. As ASIC and SoC designs move towards the gigahertz domain and inductive reactances start becoming comparable to resistances, it will become important to extend the current role of the power grid as a capacitive crosstalk shield to also provide shielding for inductive noise. Although solutions as extreme as power planes that have been used in some high-end microprocessor designs will probably not migrate to ASIC and SoC methodologies, recent work on templated and interdigitated routing in which a track is reserved for power after every few signal tracks seems promising for inductive noise handling in these contexts.

2.1 Power Grid Design: IP Block Author's Perspective

Component authors generally have very little information about the quality of the power supply at the pins of the component. A common methodology for SoC designs is for the component author and component integrator to agree ahead of time on the voltage to be applied to the component pins given the maximum current required by the component. A typical approach is to assume a fixed level, say 5%, of power degradation to the component. The component author then ensures that the component operates to specifications under this assumption. As components increase in size and are constructed hierarchically, it is the responsibility of the component author to modify the power degradation assumption in order to ensure that the assumptions of the sub-components are maintained as they are used in the larger components. Assuming uniform power degradation, results in conservative design (in many cases) because not all components see the fully-degraded power supply voltage. As designs increase in frequency, this conservatism leads to challenges in meeting timing closure on the chip, because the resulting overly conservative gate delays inherently limit the operational frequency of the design. Of course, for hold-time checks, one should assume best-case IR drops rather than the worst case ones that are used to determine the operational frequency.

Components are also generally designed assuming that power enters only from the power pins. A growing trend today is that this assumption is not always valid - power commonly flows through components as well. Since the amount of current flowing through a component cannot be determined until chip integration, it should be possible to specify current limits on the component pins to make sure electromigration limits of the component will not be violated when integrated in the design.

A model is required to represent the power grid behaviors of a component. The model is created by the component author and is applied by the chip integrator. The model must provide some visibility into the component's internals. Because IR drop issues can be investigated in either a static or dynamic sense, various models of a component are possible. In a static analysis, only power grid resistance data is required of the component. In a dynamic analysis, RC data of the component is required. The model of component power consumption must be a function of the loading on the component, so that the total power consumption of the component as well as any dynamic behaviors can be derived once the component environment is determined. The component model must also be able to specify acceptable ranges of input characteristics and output loading. Dynamic modeling will result in larger data sets to represent the model.

2.2 Power Grid Design: IP Block Integrator's Perspective

In general the design of the supply nets on chip level is based on a static DC model and guided by rules to avoid "hard to analyze" complications. Depending on the application, one might need some level of AC analysis but it is quite difficult to define a general approach.

Integrators have little knowledge of the internals of components, so they might not be aware of operating assumptions the component designer made when designing the component. A common assumption is that power comes into the component, and none passes through - this is not true in practice and has been the source of some failures.

Another common source of disconnect is related to how power ports are specified for a component. If a large component has a single long power port passing over the component, there can be questions as to how the port should be used; the various options include only a single connection at one end, connections at both ends, or additional connectivity midway as well. Since the way the component is connected to the global grid can even alter the power grid characteristics in the component (for instance, a power rung of a component can be supplemented by additional metal by the integrator), there must be some way of resolving power port usage models.

Continues...

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RAMINDERPAL SINGH, PhD, is a signal integrity expert working for IBM’s Design Kits Group. He has spent many years developing solutions for substrate noise and coupling, as well as ASIC signal integrity.