Co-design for System Acceleration

by Nedjah, Nadia; Mourelle, Luiza De Macedo

• ISBN13: 9781402055454
• ISBN10: 1402055455
• Format: Hardcover
• Copyright: 2007-05-04
• Publisher: Springer Verlag

Summary

In this book, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of this book is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration.

Table of Contents

Introduction	p. 1
The co-design methodology	p. 9
The co-design system	p. 29
VHDL model of the co-design system	p. 53
Shared memory configuration	p. 81
Dual-port memory configuration	p. 107
Cache memory configuration	p. 133
Advanced topics and further research	p. 173
Benchmark programs	p. 185
Top-level VHDL model of the co-design system	p. 191
Translating PALASM into VHDL	p. 199
VHDL version of the case study	p. 205
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