Co-Verification of Hardware and Software for ARM SoC Design

by Andrews

• ISBN13: 9780750677301
• ISBN10: 0750677309
• Edition: CD
• Format: Paperback
• Copyright: 2004-08-16
• Publisher: Elsevier Science

Summary

Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.

Table of Contents

Foreword	xiii
Preface	xv
Why Is This Book Important?	xv
Audience	xvi
Prerequisite Knowledge	xvi
About Hardware/Software Co-Verification	xvi
Acknowledgments	xvii
About the Author	xix
About Verisity	xxi
What's on the CD-ROM?	xxiii
Embedded System Verification: An Introduction	1	(24)
What's an Embedded System?	3	(2)
Embedded Systems Are Everywhere	5	(1)
Consumer Electronics	5	(1)
Wireless	5	(1)
Medical	5	(1)
Networking	5	(1)
Security	5	(1)
Imaging	5	(1)
Storage	5	(1)
Automotive	5	(1)
Design Constraints	6	(1)
Cost	6	(1)
Memory	6	(1)
Power	7	(1)
Real-Time Response	7	(1)
Performance	7	(1)
System Size	8	(1)
Reliability	8	(1)
Time-to-Market	8	(1)
Embedded Systems Decomposition	9	(1)
Microprocessors, Chips and Boards	9	(2)
Embedded System Classifications	11	(1)
Little or No Custom Hardware Design	12	(1)
A Lot of Custom Hardware -- SoB Design	12	(1)
A Lot of Custom Hardware -- SoC Design	13	(1)
Embedded System Design Process	14	(1)
Requirements	15	(1)
System Architecture	15	(1)
Microprocessor Selection	15	(1)
Hardware Design	16	(1)
Software Design	16	(1)
Hardware and Software Integration	16	(1)
Verification and Validation	16	(1)
Verification: Does it Work?	17	(1)
Validation: Did We Build the Right Thing?	17	(1)
Human Interaction	18	(2)
What is this Book About?	20	(2)
Scope and Outline	22	(3)
Hardware and Software Design Process	25	(44)
Three Components of SoC Verification	25	(1)
Verification Platform	26	(9)
Software Engineer's View of the World	35	(2)
Hardware Engineer's View of the World	37	(1)
Example	37	(2)
Software Development Tools	39	(1)
Editor	39	(1)
Source Code Revision Control	39	(1)
Compiler	40	(1)
Debugger	41	(1)
Simulator	41	(1)
Development Board	42	(1)
Integrated Development Environment (IDE)	42	(1)
Software Debugging Connections	42	(1)
JTAG	43	(1)
Stub	43	(1)
Direct Connection	44	(1)
Types of Software	44	(1)
System Initialization and HAL	44	(1)
Diagnostic Suite	45	(1)
Real-Time Operating System (RTOS)	45	(1)
Device Drivers and Application Software	45	(1)
Software Development Process	46	(6)
Hardware Development Tools	52	(1)
Editor	52	(1)
Source Code Revision Control	53	(1)
Lint Tools	54	(1)
Code Coverage	54	(1)
Debugging Tools	55	(1)
Verification Languages	55	(1)
Assertions	56	(2)
Debugging Defined	58	(1)
Memory Models	59	(2)
Microprocessor Models	61	(1)
Hardware Design Process	62	(1)
Microprocessor Review	63	(1)
Hardware and Software Interaction	64	(1)
Software Debugging Characteristics	64	(1)
Hardware Debugging Characteristics	64	(5)
SoC Verification Topics for the ARM Architecture	69	(50)
ARM Background	69	(1)
ARM Architecture	70	(1)
ARM Architectures, Families, and CPU Cores	71	(4)
Thumb Instruction Set	75	(1)
Programming Model	76	(2)
Instruction Set	78	(1)
Data Transfer Instructions	78	(1)
Coprocessor Instructions	79	(1)
Exceptions and Interrupts	80	(3)
Memory Layout and Byte Order	83	(1)
ARM Bus Interface Protocols	84	(1)
ARM7TDMI Bus Protocol	85	(4)
AMBA Specification	89	(2)
Introduction to AMBA Protocols	91	(1)
AMBA ASB	91	(1)
AMBA AHB	92	(1)
AMBA APB	92	(1)
AMBA 3.0 and AXI	92	(1)
Summary of ARM CPU Bus Interfaces	93	(1)
AHB Tutorial	94	(4)
Configuration at Reset	98	(1)
Phases of AHB Transfer	99	(1)
AHB Arbitration	99	(2)
AHB Address Phase	101	(3)
AHB Data Phase	104	(2)
AHB-Lite	106	(1)
Single-Layer and Multilayer AHB	107	(1)
ARM926EJ-S Example	107	(4)
Interrupt Signals	111	(1)
Instruction and Data Caches	111	(4)
Tightly Coupled Memory (TCM)	115	(3)
ARM Summary	118	(1)
Hardware/Software Co-Verification	119	(46)
History of Hardware/Software Co-Verification	119	(2)
Commercial Co-Verification Tools Appear	121	(3)
Co-Verification Defined	124	(1)
Definition	124	(1)
Benefits of Co-Verification	125	(1)
Project Schedule Savings	125	(2)
Co-Verification Enables Learning by Providing Visibility	127	(1)
Co-Verification Improves Communication	127	(1)
Co-Verification versus Co-Simulation	128	(1)
Co-Verification versus Co-Design	128	(1)
Is Co-Verification Really Necessary?	129	(1)
Co-Verification Methods	129	(1)
Native Compiling Software	130	(1)
Instruction Set Simulation	130	(1)
Hardware Stubs	131	(1)
Real-Time Operating System (RTOS) Simulator	132	(1)
Microprocessor Evaluation Board	132	(1)
Waveforms, Log Files, and Disassembly	133	(1)
A Sample of Co-Verification Methods	134	(1)
Host-Code Mode with Logic Simulation	134	(3)
Instruction Set Simulation with Logic Simulation	137	(3)
C Simulation	140	(4)
RTL Model of CPU with Software Debugging	144	(3)
Hardware Model with Logic Simulation	147	(2)
Evaluation Board with Logic Simulation	149	(1)
In-Circuit Emulation	150	(3)
FPGA Prototype	153	(1)
Co-Verification Metrics	154	(1)
Performance	155	(1)
Verification Accuracy	155	(3)
AHB Arbitration and Cycle Accuracy Issues	158	(2)
Modeling Summary	160	(1)
Synchronization	161	(1)
Types of Software	162	(1)
Other Metrics	162	(3)
Advanced Hardware/Software Co-Verification	165	(32)
Direct Access to Simulation Memories	165	(6)
Memory Optimizations and Performance	171	(4)
Modes of Synchronization	175	(2)
Interprocess Communication	177	(3)
Mixing HDL and C Models	180	(3)
Implicit Access	183	(3)
Save and Restart	186	(2)
Post-Processing Software Debugging Techniques	188	(5)
Embedded Software Tool Issues	193	(1)
Debugging Co-Verification Issues	194	(3)
Hardware Verification Environment and Co-Verification	197	(32)
Bus Monitor	197	(10)
Protocol Checking	207	(1)
Aligned Addresses	207	(1)
Issuing Idle Transfers	207	(1)
Assertions	208	(1)
Assertion Definitions	208	(2)
Assertion Approaches	210	(1)
Declarative Assertions	210	(2)
Procedural Assertions	212	(1)
Formal Property Language	212	(1)
Pseudo-Comment Directives	213	(1)
Post-Processing Simulation History	213	(1)
Assertions for Simulation Acceleration and Emulation	214	(1)
Testbenches Using Bus Functional Models	215	(1)
Directed Tests	216	(1)
Constrained Random Tests	217	(1)
Testbench Architecture	218	(2)
Functional Coverage	220	(1)
Compliance Suite	221	(1)
Software Verification	221	(1)
Software Print Statements	222	(5)
Summary	227	(2)
Methodology for an Example ARM SoC	229	(24)
SoC Methodology Difficulty	230	(1)
Verification Efficiency	231	(1)
The Debugging Loop	232	(2)
Co-Verification Methodology	234	(1)
System Initialization and HAL Development	235	(1)
Diagnostics	235	(1)
RTOS and Device Drivers	236	(1)
Application Software	236	(1)
Testbench Development	236	(1)
Three Verification Phases	237	(2)
Example of ARM Verification Flow	239	(1)
Block and Subsystem Verification	239	(1)
Initial System Integration	240	(2)
Focused Hardware Verification	242	(1)
Hardware/Software Co-Verification	243	(1)
System Software Testing	244	(2)
The Co-Verification Engineer	246	(2)
Conclusion	248	(1)
Methodology Gridlock	249	(4)
Afterward	253	(2)
Index	255