Defect Oriented Testing for CMOS Analog and Digital Circuits

by Manoj Sachdev

• ISBN13: 9780792380832
• ISBN10: 0792380835
• Format: Nonspecific Binding
• Copyright: 2013-06-29
• Publisher: Springer Nature

Summary

Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. 'A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal

Table of Contents

Foreword	xi	(2)
Preface	xiii
CHAPTER 1 Introduction	1	(14)
1.1 The Test Complexity	1	(2)
1.2 Quality and Reliability Awareness	3	(2)
1.3 Building Quality and Reliability	5	(2)
1.4 Objectives of this book	7	(2)
1.5 Outline of the book	9	(3)
References	12	(3)
CHAPTER 2 Digital CMOS Fault Modeling and Inductive Fault Analysis	15	(50)
2.1 Objectives of Fault Modeling	15	(2)
2.2 Levels of Testing	17	(2)
2.3 Levels of fault Modeling	19	(27)
2.4 Inductive Fault Analysis	46	(8)
2.5 Conclusion	54	(1)
References	55	(10)
CHAPTER 3 Defects in Logic Circuits and Their Test Implications	65	(30)
3.1 Introduction	65	(2)
3.2 Stuck-at Faults and Manufacturing Defects	67	(14)
3.3 IFA Experiments on Standard Cells	81	(4)
3.4 IDDQ Versus Voltage Testing	85	(4)
3.5 Defect Classes and their Testing	89	(2)
3.6 Conclusion	91	(1)
References	92	(3)
CHAPTER 4 Testing Defects in Sequential Circuits	95	(38)
4.1 Introduction	95	(2)
4.2 Undetected Defects	97	(3)
4.3 The Local Solution	100	(3)
4.4 The Transparent Scan	103	(10)
4.5 Testable Flip-flop Configurations	113	(15)
4.6 Conclusion	128	(2)
References	130	(3)
CHAPTER 5 Defect Oriented RAM Testing and Current Testable RAMs	133	(72)
5.1 Introduction	133	(2)
5.2 Traditional RAM Fault Models	135	(2)
5.3 Development of a Defect based SRAM Fault Model	137	(5)
5.4 Development of a Defect based DRAM Fault Model	142	(15)
5.5 Address Decoder faults	157	(16)
5.6 Parallel Testing of RAMs	173	(5)
5.7 IDDQ Based RAM Parallel Testing	178	(18)
5.8 Conclusion	196	(3)
References	199	(6)
CHAPTER 6 Testing Defects in Programmable Logic Circuits	205	(38)
6.1 Introduction	205	(2)
6.2 Evolution of Programmable Circuits	207	(3)
6.3 PLA Test Complexity	210	(3)
6.4 Testability Schemes for PLAs	213	(4)
6.5 BIST for PLAs	217	(5)
6.6 Detection of Realistic Faults in PLAs	222	(7)
6.7 IDDQ Testable Dynamic PLAs	229	(8)
6.8 Conclusion	237	(1)
References	238	(5)
CHAPTER 7 Defect Oriented Analog Testing	243	(54)
7.1 Introduction	243	(1)
7.2 Analog Test Complexity	244	(2)
7.3 Previous Work	246	(3)
7.4 Defect Based Realistic Fault Dictionary	249	(11)
7.5 A Case Study	260	(3)
7.6 Results	263	(10)
7.7 IFA based Fault Grading and DfT for Analog Circuits	273	(12)
7.8 High Level Analog Fault Models	285	(4)
7.9 Conclusion	289	(2)
References	291	(6)
CHAPTER 8 Conclusion	297	(8)
8.1 The Test Complexity	297	(1)
8.2 Defect Oriented Testing	298	(3)
8.3 Future Directions	301	(1)
References	302	(3)
INDEX	305