Design for Manufacturability Through Design-process Integration II

by Singh, Vivek K.; Rieger, Michael L.

• ISBN13: 9780819471109
• ISBN10: 0819471100
• Format: Paperback
• Copyright: 2008-04-09
• Publisher: Society of Photo Optical

Summary

Proceedings of SPIE present the original research papers presented at SPIE conferences and other high-quality conferences in the broad-ranging fields of optics and photonics. These books provide prompt access to the latest innovations in research and technology in their respective fields. Proceedings of SPIE are among the most cited references in patent literature.

Table of Contents

DfM, the teenage years

Intel design for manufacturing and evolution of design rules

Automatic hotspot classification using pattern-based clustering

Effective learning and feedback to designers through design and wafer inspection integration

Rigorous CMP and electroplating simulations for DFM applications

Global and local factors of on-chip variation of gate length

Layout verification in the era of process uncertainty: target process variability bands vs. actual process variability bands

Context analysis and validation of lithography induced systematic variations in 65nm designs

Low-k[subscript 1] logic design using gridded design rules

DfM lessons learned from altPSM design

Yield aware design of gate layer for 45 nm CMOS-ASIC using a high-NA dry KrF systems

Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection

Layout optimization based on a generalized process variability model

Manufacturing for design: a novel interconnect optimization method

Shaping gate channels for improved devices

A routing clean-up methodology for improvement of defect and lithography related yield

Analysis of systematic variation and impact on circuit performance

VARAN: variability analysis for memory cell robustness

Implementation of silicon-validated variability analysis and optimization for standard cell libraries

Microprocessor chip timing analysis using extraction of simulated silicon-calibrated contours

Hypersensitive parameter-identifying ring oscillators for lithography process monitoring

Systematic yield estimation method applying lithography simulation

Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell

Predicting yield using model based OPC verification: calibrated with electrical test data

Exposure tool specific post-OPC verification

A procedure to back-annotate process induced layout dimension changes into the post layout simulation netlist

Predicting conversion time of circuit design file by artificial neural networks

System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator

An extraction of repeating patterns from OPCed layout data

Accurate model base verification scheme to eliminate hotspots and manage warmspots

ACLV- and process-window-aware extraction of transistor parameters using litho-friendly design (LfD) methodologies

Device performance-based OPC for optimal circuit performance and mask cost reduction

Concurrent development methodology from design rule to OPC in 45-nm node logic device

Improvement on OPC completeness through pre-OPC hot spot detection and fix

DFM application on dual tone sub 50nm device

SEM contour-based model OPC calibrated with optically sensitive patterns

Hot spot management with die-to-database wafer inspection system

32nm design rule evaluation through virtual patterning

A new robust process window qualification (PWQ) technique to perform systematic defect characterization to enlarge the lithographic process window using a die-to-database verification tool (NGR2100)

Continuous process window modeling for process variation aware OPC and lithography verification

Using composite gratings for optical system characterization through scatterometry

Rules based process window OPC

RET selection using rigorous physics-based computational lithography

APF pitch-halving for 22nm logic cells using gridded design rules

Site portability and extrapolative accuracy of a predictive resist model

A comprehensive model of process variability for statistical timing optimization

Application of layout DOE in RET flow

Impact of gate line edge roughness on double-gate FinFET performance variability

Validation and application of a mask model for inverse lithography

Cell-based OPC with standard-cell fill insertion

Process variation in metal-oxide-metal (MOM) capacitors

Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability

A method of obtaining optical lithography friendly layout using a model for first level defects

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Layout patterning check for DFM

Design based binning for litho qualification and process window qualification

DFM software for photomask production and qualification of its accuracy and functionality

Electrically driven optical proximity correction

Author Index

Table of Contents provided by Blackwell. All Rights Reserved.