Design of Multi-Bit Delta-Sigma A/d Converters

by Geerts, Yves; Steyaert, Michiel; Sansen, Willy M. C.

• ISBN13: 9781402070785
• ISBN10: 1402070780
• Format: Hardcover
• Copyright: 2002-05-01
• Publisher: Kluwer Academic Pub

Summary

Design of Multi-Bit Delta-Sigma A/D Converters discusses both architecture and circuit design aspects of Delta-Sigma A/D converters, with a special focus on multi-bit implementations. The emphasis is on high-speed high-resolution converters in CMOS for ADSL applications, although the material can also be applied for other specification goals and technologies. Design of Multi-Bit Delta-Sigma A/D Converters starts with a general introduction of the concepts of Delta-Sigma converters. A wide variety of architectures are discussed, ranging from single-loop to cascaded and various multi-bit topologies. These topologies are optimized to obtain stable converters with a high accuracy. A clear overview is provided of the maximum achievable performance of each topology, which allows a designer to select the optimal architecture for a certain specification. Special attention is paid to multi-bit architectures and possible solutions for the linearity problem of the DA converter in the feedback loop of converters. Several circuit design aspects of multi-bit Delta-Sigma converters are discussed. Various models are provided for a wide range of linear and non-linear circuit imperfections, which can degrade the performance of the converter. These models allow the designer to determine the required specifications for the different building blocks and form the basis of a systematic design procedure. The presented material is combined in a concluding chapter, which illustrates the systematic design procedure for two high-performance converters. Design of Multi-Bit Delta-Sigma A/D Converters provides a clear comparison of architectures and yields insight into the influence of the most important circuit non-idealities. It will allow you to design robust and high-performance Delta-Sigma AD converters in a shorter time. It is essential reading for analog design engineers and researchers in the field of AD converters and it is also suitable as a text for an advanced course on the subject.

Table of Contents

Abstract	p. I
List of Symbols and Abbreviations	p. III
Introduction	p. 1
Motivation and Applications	p. 1
Asymmetric Digital Subscriber Line (ADSL)	p. 2
Wideband Receiver	p. 4
The Presented Work	p. 4
Architecture Study of Delta-Sigma Converters	p. 7
Introduction	p. 7
Operation Principle of Delta-Sigma Converters	p. 8
Nyquist-Rate ADC	p. 8
Oversampled ADC	p. 14
Oversampling Combined with Noise-Shaping: a [Delta Sigma] ADC	p. 18
Definition of Performance Metrics for a [Delta Sigma] ADC	p. 22
Ideal Performance of a [Delta Sigma] ADC	p. 25
Optimal Coefficients for [Delta Sigma] Converters	p. 29
Single-Loop Topologies	p. 30
First-Order [Delta Sigma] Converters	p. 33
Second-Order [Delta Sigma] Converters	p. 35
Third-order [Delta Sigma] Converters	p. 38
Fourth and Higher-Order [Delta Sigma] Converters	p. 42
Other Single-Loop Topologies	p. 42
Cascaded Topologies	p. 43
Performance Comparison of [Delta Sigma] Topologies	p. 53
Continuous-Time Implementations	p. 56
Linearity Issues of Multi-Bit [Delta Sigma] Converters	p. 61
Trimming and Analog Calibration Techniques	p. 67
Digital Calibration Techniques	p. 68
Dual-Quantization Techniques	p. 68
Leslie-Singh Architecture	p. 69
Single-Loop Dual-Quantization Architecture	p. 71
Cascaded Dual-Quantization Architecture	p. 73
Dynamic Element Matching Techniques	p. 74
Randomization	p. 77
Clocked Averaging (CLA)	p. 79
Individual Level Averaging (ILA)	p. 81
Data Weighted Averaging (DWA)	p. 81
Bi-directional Data Weighted Averaging (biDWA)	p. 86
Partitioned Data Weighted Averaging (PDWA)	p. 88
Data Directed Scrambling (DDS)	p. 88
Second-Order Data Weighted Averaging (DWA 02)	p. 91
Vector-Quantizer Structures	p. 92
Noise-Shaped DEM with Tree-Structures	p. 94
Comparison	p. 96
Conclusion	p. 96
Design Considerations for Multi-Bit [Delta Sigma] Converters	p. 99
Introduction	p. 99
Clock-Jitter	p. 100
Nyquist-Rate AD Converters	p. 100
Discrete-Time [Delta Sigma] Converters	p. 100
Continuous-Time [Delta Sigma] converters	p. 101
Comparison	p. 104
Discrete-Time versus Continuous-Time [Delta Sigma] Converters	p. 105
System Level Considerations	p. 108
Single Ended versus Differential Implementations	p. 108
Implementations of Integrators with Single-Bit and Multi-Bit Feedback	p. 109
Signal Swings	p. 112
Non-Ideal Switched-Capacitor Integrator	p. 112
Finite Gain of the OTA	p. 115
Dominant Closed-Loop Pole of the OTA	p. 117
Switch Resistance and Dominant Closed-Loop Pole of the OTA	p. 119
Slew-Rate and Dominant Closed-Loop Pole of the OTA	p. 122
Full Model Including Switch Resistance, Slew-Rate and Dominant Closed-Loop Pole	p. 126
Other Non-Idealities in a Switched-Capacitor Integrator	p. 128
Clock Feedthrough and Charge Injection	p. 129
Coefficient Mismatch	p. 130
Non-Linear Capacitances	p. 130
Non-Linear OTA Gain	p. 133
Non-Linear Switch Resistance	p. 135
Non-Idealities of the DAC and the Quantizer	p. 141
Non-Idealities of the DAC	p. 141
Non-Idealities of the Quantizer	p. 142
Noise Analysis	p. 143
Noise Contribution of the Different Integrators	p. 144
Equivalent Input Noise of a Switched-Capacitor Integrator	p. 145
Power Estimation and Design Considerations	p. 149
Conclusion	p. 158
Implementations	p. 159
Introduction	p. 159
A 15-bit 2.2MS/s 3.3V Cascaded [Delta Sigma] converter	p. 159
Topology Selection and System Level Design	p. 160
Circuit Level Design	p. 165
Design of the Integrator	p. 165
Design of the Quantizer	p. 169
Design of the Clock Generator	p. 171
Layout and Measurement Results	p. 172
A 16-bit 2.5 MS/s 5V Multi-Bit [Delta Sigma] Converter	p. 176
Topology Selection and System Level Design	p. 176
Circuit Level Design	p. 178
Implementation of the Data Weighted Averaging Algorithm	p. 180
Design of the Quantizer	p. 182
Design of the DAC and the Integrator	p. 184
Layout and Measurement Results	p. 190
Performance Comparison	p. 195
Conclusion	p. 199
Conclusions	p. 201
A Switched-Capacitor Integrator Including Slew-Rate Effects	p. 203
Charges on the Capacitors	p. 204
Calculations for the Sampling Phase	p. 205
Linear Settling	p. 206
Slewing during an Entire Clock Phase	p. 206
Slewing followed by Linear Settling	p. 207
Calculations for the Integration Phase	p. 207
Linear Settling	p. 208
Slewing during an Entire Clock Phase	p. 208
Slewing followed by Linear Settling	p. 209
Conclusion	p. 209
Bibliography	p. 211
Index	p. 223
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