(Note:Each chapter begins with an Outline, Objectives, and an Introduction, and concludes with a Summary, Glossary, Problems, Schematic Interpretation Problems, Electronics Workbench Exercises, and Answers to Review Questions.) | |
Number Systems and Codes | |
Digital Versus Analog | |
Digital Representations of Analog Quantities | |
Decimal Numbering System (Base 10) | |
Binary Numbering System (Base 2) | |
Decimal-to-Binary Conversion | |
Octal Numbering System (Base 8) | |
Octal Conversions | |
Hexadecimal Numbering System (Base 16) | |
Hexadecimal Conversions | |
Binary-Coded-Decimal System | |
Comparison of Numbering Systems | |
The ASCII Code | |
Applications of the Numbering Systems | |
Digital Electronic Signals and Switches | |
Digital Signals | |
Clock Waveform Timing | |
Serial Representation | |
Parallel Representation | |
Switches in Electronic Circuits | |
A Relay as a Switch | |
A Diode as a Switch | |
A Transistor as a Switch | |
The TTL Integrated Circuit | |
MultiSIM Simulation of Switching Circuits | |
The CMOS Integrated Circuit | |
Surface-Mount Devices | |
Basic Logic Gates | |
The AND Gate | |
The OR Gate | |
Timing Analysis | |
Enable and Disable Functions | |
Using IC Logic Gates | |
Introduction to Troubleshooting Techniques | |
The Inverter | |
The NAND Gate | |
The NOR Gate | |
Logic Gate Waveform Generation | |
Using IC Logic Gates | |
Summary of the Basic Logic Gates and IEEE/IEC Standard Logic Symbols | |
Programmable Logic Devices: Altera and Xilinx CPLDs and FPGAs | |
PLD Design Flow | |
PLD Architecture | |
Using PLDs to Solve Basic Logic Designs | |
CPLD Problems | |
Boolean Algebra and Reduction Techniques | |
Combinational Logic | |
Boolean Algebra Laws and Rules | |
Simplification of Combinational Logic Circuits Using Boolean Algebra | |
De Morgan's Theorem | |
The Universal Capability of NAND and NOR Gates | |
AND-OR-INVERT Gates for Implementing Sum-of-Products Expressions | |
Karnaugh Mapping | |
System Design Applications | |
CPLD Design Applications | |
CPLD Problems | |
Exclusive-OR and Exclusive-NOR Gates | |
The Exclusive-OR Gate | |
The Exclusive-NOR Gate | |
Parity Generator/Checker | |
System Design Applications | |
CPLD Design Applications | |
CPLD Problems | |
Arithmetic Operations and Circuits | |
Binary Arithmetic | |
Two's-Complement Representation | |
Two's-Complement Arithmetic | |
Hexadecimal Arithmetic | |
BCD Arithmetic | |
Arithmetic Circuits | |
Four-Bit Full-Adder ICs | |
System Design Applications | |
Arithmetic/Logic Units | |
CPLD Design Applications | |
CPLD Problems | |
Code Converters, Multiplexers, and Demultiplexers | |
Comparators | |
Decoding | |
Encoding | |
Code Converters | |
Multiplexers | |
Demultiplexers | |
System Design Applications | |
CPLD Design Applications | |
CPLD Problems | |
Logic Families and Their Characteristics | |
The TTL Family | |
TTL Voltage and Current Ratings | |
Other TTL Considerations | |
Improved TTL Series | |
The CMOS Family | |
Emitter-Coupled Logic | |
Comparing Logic Families | |
Interfacing Logic Families | |
Flip-Flops and Registers | |
S-RFlip-Flop | |
GatedS-RFlip-Flop | |
GatedDFlip-Flop | |
Integrated-Circuit | |
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