Digital Signal Processing With Field Programmable Gate Arrays

by Meyer-Baese, Uwe

• ISBN13: 9783540726128
• ISBN10: 3540726128
• Edition: 3rd
• Format: Hardcover
• Copyright: 2008-02-01
• Publisher: SPRINGER

Summary

Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms. So the efficient implementation of these algorithms is critical and is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 40 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, advanced algorithms with high future potential, and adaptive filters. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices, while the accompanying CD-ROM contains the examples in VHDL and Verilog code as well as the newest Altera "Quartus II web edition" software. This edition has a new chapter on microprocessors, new sections on special functions using MAC calls, intellectual property core design and arbitrary sampling rate converters, and over 100 new exercises.

Table of Contents

Preface	p. VII
Preface to Second Edition	p. XI
Preface to Third Edition	p. XIII
Introduction	p. 1
Overview of Digital Signal Processing (DSP)	p. 1
FPGA Technology	p. 3
Classification by Granularity	p. 3
Classification by Technology	p. 6
Benchmark for FPLs	p. 7
DSP Technology Requirements	p. 10
FPGA and Programmable Signal Processors	p. 12
Design Implementation	p. 13
FPGA Structure	p. 18
The Altera EP2C35F672C6	p. 22
Case Study: Frequency Synthesizer	p. 29
Design with Intellectual PropertyCores	p. 35
Exercises	p. 42
Computer Arithmetic	p. 53
Introduction	p. 53
Number Representation	p. 54
Fixed-Point Numbers	p. 54
Unconventional Fixed-Point Numbers	p. 57
Floating-Point Numbers	p. 71
Binary Adders	p. 74
PipelinedAdders	p. 76
Modulo Adders	p. 80
Binary Multipliers	p. 82
Multiplier Blocks	p. 87
Binary Dividers	p. 91
Linear Convergence Division Algorithms	p. 93
Fast Divider Design	p. 98
Array Divider	p. 103
Floating-Point Arithmetic Implementation	p. 104
Fixed-point to Floating-Point Format Conversion	p. 105
Floating-Point to Fixed-Point Format Conversion	p. 106
Floating-Point Multiplication	p. 107
Floating-PointAddition	p. 108
Floating-PointDivision	p. 110
Floating-Point Reciprocal	p. 112
Floating-Point Synthesis Results	p. 114
Multiply-Accumulator (MAC) and Sum of Product (SOP)	p. 114
Distributed Arithmetic Fundamentals	p. 115
Signed DA Systems	p. 118
Modified DA Solutions	p. 120
Computation of Special Functions Using CORDIC	p. 120
CORDIC Architectures	p. 125
Computation of Special Functions using MAC Calls	p. 130
ChebyshevApproximations	p. 131
Trigonometric Function Approximation	p. 132
Exponential and Logarithmic Function Approximation	p. 141
Square Root Function Approximation	p. 148
Exercises	p. 154
Finite Impulse Response (FIR) Digital Filters	p. 165
Digital Filters	p. 165
FIRTheory	p. 166
FIR Filter with Transposed Structure	p. 167
SymmetryinFIRFilters	p. 170
Linear-phaseFIRFilters	p. 171
DesigningFIRFilters	p. 172
Direct Window Design Method	p. 173
EquirippleDesignMethod	p. 175
Constant Coefficient FIR Design	p. 177
Direct FIR Design	p. 178
FIRFilterwithTransposedStructure	p. 182
FIRFiltersUsingDistributedArithmetic	p. 189
IP CoreFIRFilterDesign	p. 204
Comparison of DA- and RAG-Based FIR Filters	p. 207
Exercises	p. 209
Infinite Impulse Response (IIR) Digital Filters	p. 215
IIRTheory	p. 218
IIR Coefficient Computation	p. 221
Summary of Important IIR Design Attributes	p. 223
IIR Filter Implementation	p. 224
Finite Wordlength Effects	p. 228
Optimization of the Filter Gain Factor	p. 229
Fast IIR Filter	p. 230
Time-domain Interleaving	p. 230
Clustered and Scattered Look-Ahead Pipelining	p. 233
IIR Decimator Design	p. 235
Parallel Processing	p. 236
IIR Design Using RNS	p. 239
Exercises	p. 240
Multirate Signal Processing	p. 245
Decimation and Interpolation	p. 245
Noble Identities	p. 246
Sampling Rate Conversion by Rational Factor	p. 248
Polyphase Decomposition	p. 249
RecursiveIIRDecimator	p. 254
Fast-running FIR Filter	p. 254
Hogenauer CIC Filters	p. 256
Single-Stage CIC Case Study	p. 257
Multistage CIC Filter Theory	p. 259
Amplitude and Aliasing Distortion	p. 264
Hogenauer Pruning Theory	p. 266
CIC RNS Design	p. 272
Multistage Decimator	p. 273
Multistage Decimator Design Using Goodman-Carey Half-band Filters	p. 274
Frequency-Sampling Filters as Bandpass Decimators	p. 277
Design ofArbitrarySampling Rate Converters	p. 280
Fractional Delay Rate Change	p. 284
Polynomial Fractional Delay Design	p. 290
B-Spline-Based Fractional Rate Changer	p. 296
MOMS Fractional Rate Changer	p. 301
Filter Banks	p. 308
Uniform DFT Filter Bank	p. 309
Two-channel Filter Banks	p. 313
Wavelets	p. 328
The Discrete Wavelet Transformation	p. 332
Exercises	p. 335
Fourier Transforms	p. 343
The Discrete Fourier Transform Algorithms	p. 344
Fourier Transform Approximations Using the DFT	p. 344
Properties of the DFT	p. 346
The Goertzel Algorithm	p. 349
The Bluestein Chirp-z Transform	p. 350
The Rader Algorithm	p. 353
The Winograd DFT Algorithm	p. 359
The Fast Fourier Transform (FFT) Algorithms	p. 361
The Cooley-Tukey FFT Algorithm	p. 363
The Good-Thomas FFT Algorithm	p. 373
The Winograd FFT Algorithm	p. 375
Comparison of DFT and FFT Algorithms	p. 379
IP Core FFT Design	p. 381
Fourier-Related Transforms	p. 385
Computing the DCT Using the DFT	p. 387
Fast Direct DCT Implementation	p. 388
Exercises	p. 391
Advanced Topics	p. 401
Rectangular and Number Theoretic Transforms (NTTs)	p. 401
Arithmetic Modulo 26 ± 1	p. 403
Efficient Convolutions Using NTTs	p. 405
Fast Convolution Using NTTs	p. 405
Multidimensional Index Maps	p. 409
Computing the DFT Matrix with NTTs	p. 411
Index Maps for NTTs	p. 413
Using Rectangular Transforms to Compute the DFT	p. 416
Error Control and Cryptography	p. 418
Basic Concepts from Coding Theory	p. 419
Block Codes	p. 424
Convolutional Codes	p. 428
Cryptography Algorithms for FPGAs	p. 436
Modulation and Demodulation	p. 453
Basic Modulation Concepts	p. 453
Incoherent Demodulation	p. 457
Coherent Demodulation	p. 463
Exercises	p. 472
Adaptive Filters	p. 477
Application of Adaptive Filter	p. 478
Interference Cancellation	p. 478
Prediction	p. 479
Inverse Modeling	p. 479
Identification	p. 480
Optimum Estimation Techniques	p. 481
The Optimum Wiener Estimation	p. 482
The Widrow-Hoff Least Mean Square Algorithm	p. 486
Learning Curves	p. 493
Normalized LMS (NLMS)	p. 496
Transform Domain LMS Algorithms	p. 498
Fast-Convolution Techniques	p. 498
Using Orthogonal Transforms	p. 500
Implementation of the LMS Algorithm	p. 503
Quantization Effects	p. 504
FPGA Design of the LMS Algorithm	p. 504
Pipelined LMS Filters	p. 507
Transposed Form LMS Filter	p. 510
Design of DLMS Algorithms	p. 511
LMS Designs using SIGNUM Function	p. 515
Recursive Least Square Algorithms	p. 518
RLS with Finite Memory	p. 521
Fast RLS Kalman Implementation	p. 524
The Fast a Posteriori Kalman RLS Algorithm	p. 529
Comparison ofLMS and RLS Parameters	p. 530
Exercises	p. 532
Microprocessor Design	p. 537
History of Microprocessors	p. 537
Brief History of General-Purpose Microprocessors	p. 538
Brief History of RISC Microprocessors	p. 540
Brief History of PDSPs	p. 541
Instruction Set Design	p. 544
Addressing Modes	p. 544
Data Flow: Zero-,One-, Two- or Three-Address Design	p. 552
Register File and Memory Architecture	p. 558
Operation Support	p. 562
Next Operation Location	p. 565
Software Tools	p. 566
Lexical Analysis	p. 567
Parser Development	p. 578
FPGA Microprocessor Cores	p. 588
Hardcore Microprocessors	p. 589
Softcore Microprocessors	p. 594
Case Studies	p. 605
T-RISC Stack Microprocessors	p. 605
LISA Wavelet Processor Design	p. 610
Nios FFT Design	p. 625
Exercises	p. 634
References	p. 645
Verilog Source Code 2001	p. 661
VHDL and Verilog Coding	p. 729
ListofExamples	p. 731
LibraryofParameterizedModules(LPM)	p. 733
The Parameterized Flip-Flop Megafunction (lpm_ff)	p. 733
The Adder/Subtractor Megafunction	p. 737
The Parameterized Multiplier Megafunction (lpm_mult)	p. 741
The Parameterized ROM Megafunction (lpm_rom)	p. 746
The Parameterized Divider Megafunction (lpm_divide)	p. 749
The Parameterized RAM Megafunction (lpm_ram_dq)	p. 751
Glossary	p. 755
CD-ROM File: "1readme.ps"	p. 761
Index	p. 769
Table of Contents provided by Publisher. All Rights Reserved.