Digital Signal Processing for Multimedia Systems

by Parhi; Keshab K.

• ISBN13: 9780824719241
• ISBN10: 0824719247
• Edition: 1st
• Format: Hardcover
• Copyright: 1999-03-11
• Publisher: CRC Press

Summary

Addresses a wide selection of multimedia applications, programmable & custom architectures for the implementations of multimedia systems, & arithmetic architectures & design methodologies. Covers recent applications of digital signal processing algorithms in multimedia, presents high-speed & low-priority binary & finite field arithmetic architectures, details VHDL-based implementation approaches, & more.

Table of Contents

Series Introduction	iii
K. J. Ray Liu
Preface	v
Part I System Applications
Multimedia Signal Processing Systems	1	(16)
Takao Nishitani
Introduction	1	(3)
Digitization of Audio and Video	4	(6)
Multimedia Services	10	(2)
Hardware Implementation	12	(5)
References	16	(1)
Video Compression	17	(26)
Keshab K. Parhi
Introduction	17	(1)
Entropy Coding Techniques	18	(4)
Transform Coding Techniques	22	(9)
Motion Estimation/Compensation	31	(2)
MPEG-2 Digital Video Coding Standard	33	(5)
Computation Demands in Video Processing	38	(2)
Conclusions	40	(3)
References	40	(3)
Audio Compression	43	(24)
Akihiko Sugiyama
Masahiro Iwadare
Standardization Activities of HiFi Audio Coding	43	(1)
MPEG Audio Algorithm Structure	44	(7)
MPEG-1 Audio Algorithm Structure	51	(9)
MPEG-2 Audio Algorithm Structure	60	(4)
Future Work	64	(3)
System Synchronization	67	(16)
Hidenobu Harasaki
Introduction	67	(1)
System Clock Synchronization Overview	68	(3)
Clock Transmission Methods	71	(1)
Multiplexing and Demultiplexing	72	(3)
MPEG-2 System	75	(2)
Network Adaption	77	(2)
ATM Adaption for Low Bitrate Speech	79	(1)
Multipoint Communication	79	(1)
Resilience for Bit Error and Cell/Packet Losses	80	(1)
Future Work	81	(2)
References	81	(2)
Digital Versatile Disk	83	(26)
Shin-ichi Tanaka
Kazuhiro Tsuga
Masayuki Kozuka
Introduction	83	(1)
Physical Format	84	(9)
File System Layer	93	(1)
Application Layer	94	(15)
References	108	(1)
High-Speed Data Transmission over Twisted Pair Channels	109	(30)
Naresh R. Shanbhag
Introduction	109	(1)
Preliminaries	110	(3)
The Channel	113	(3)
The Carrierless Amplitude/Phase (CAP) Modulation Scheme	116	(6)
The Hilbert Transform Based FSLE Architecture	122	(5)
Strength Reduced Adaptive Filter	127	(4)
Design Examples	131	(4)
Conclusions	135	(4)
Cable Modems	139	(38)
Alan Gatherer
Introduction	139	(1)
Cable System Topologies for Analog Video Distribution	140	(5)
An Overview of a Cable Modem System	145	(7)
Channel Model	152	(7)
Downstream PHY	159	(9)
Upstream PHY	168	(3)
Acknowledgements	171	(6)
References	171	(6)
Wireless Communication Systems	177	(48)
Elvino S. Sousa
Introduction	177	(1)
Amps	178	(2)
Digital Wireless Systems	180	(10)
IS-54/136	190	(4)
GSM	194	(4)
CDMA	198	(16)
Power Control	214	(3)
Hand-off Processes	217	(3)
Multimedia Services	220	(1)
Conclusions	221	(4)
References	222	(3)
Part II Programmable and Custom Architectures and Algorithms
Programmable DSPs	225	(20)
Wanda K. Gass
David H. Bartley
Introduction	225	(1)
History of Programmable DSPs	225	(1)
Architecture Overview	226	(2)
Hard Real-Time Processing	228	(1)
Low Cost	229	(9)
Minimum Code Size	238	(2)
Low Power Dissipation	240	(1)
Specialization	241	(1)
Summary	241	(4)
References	242	(3)
RISC, Video and Media DSPs	245	(28)
Ichiro Kuroda
Introduction	245	(2)
Media MPU	247	(13)
Video DSP and Media Processors	260	(6)
Comparison of Architectures	266	(3)
Conclusions	269	(4)
Wireless Digital Signal Processors	273	(26)
Ingrid Verbauwhede
Mihran Touriguian
Introduction	273	(1)
Digital Wireless Communications	273	(11)
Wireless Digital Signal Processors	284	(4)
A Domain Specific DSP Core: Lode	288	(8)
Conclusions	296	(3)
References	297	(2)
Motion Estimation System Design	299	(30)
Yasushi Ooi
Introduction	299	(2)
Block-Matching Motion Estimation	301	(3)
Motion Vector Search Algorithms	304	(5)
Circuit Architectures for Motion Vector Search	309	(8)
Video Encoder LSI Implementations	317	(6)
Motion Estimation--Other Techniques	323	(2)
Concluding Remarks	325	(4)
References	325	(4)
Wavelet VLSI Architectures	329	(26)
Tracy C. Denk
Keshab K. Parhi
Introduction	329	(1)
Introduction to Wavelet Transforms	329	(4)
The One-Dimensional DWT	333	(15)
Architectures for 2-D DWT	348	(1)
Summary	349	(6)
References	351	(4)
DCT Architectures	355	(30)
Ching Yu-Hung
Introduction	355	(1)
DCT Algorithms	356	(9)
DCT Architectures	365	(11)
Conclusion and Future Trends	376	(9)
References	378	(7)
Lossless Coders	385	(32)
Ming-Ting Sun
Sachin G. Deshpande
Jenq-Neng Hwang
Introduction	385	(1)
Huffman-Based Lossless Coding	386	(3)
Implementation of Huffman-Based Encoders and Decoders	389	(5)
Arithmetic Coding	394	(4)
Implementation of Arithmetic Coders	398	(14)
Systems Issues	412	(1)
Summary	413	(4)
References	413	(4)
Viterbi Decoders: High Performance Algorithms and Architectures	417	(1)
Herbert Dawid
Olaf Joeressen
Heinrich Meyr
Introduction	417	(2)
The Viterbi Algorithm	419	(9)
The Transition Metric Unit	428	(4)
The Add--Compare--Select Unit	432	(17)
Synchronization of Coded Streams	449	(3)
Recent Developments	452	(1)
References	453	(8)
A Review of Watermarking Principles and Practices	461	(1)
Ingemar J. Cox
Matt L. Miller
Jean-Paul M. G. Linnartz
Ton Kalker
Introduction	461	(2)
Framework	463	(2)
Properties of Watermarks	465	(6)
Example of a Watermarking Method	471	(1)
Robustness to Signal Transformations	472	(10)
Tamper Resistance	482	(1)
Summary	482	(5)
References	482	(5)
Systolic RLS Adaptive Filtering	487	(32)
K. J. Ray Liu
An-Yeu Wu
Introduction	487	(2)
Square Root and Division Free Givens Rotation Algorithm	489	(2)
Square Root and Division Free RLS Algorithms and Architectures	491	(6)
Square Root and Division Free CRLS Algorithms and Architectures	497	(6)
Split RLS Algorithm and Architecture	503	(4)
Performance Analysis and Simulations of Split RLS	507	(5)
Split RLS with Orthogonal Preprocessing	512	(2)
Conclusions	514	(5)
References	517	(2)
Part III Advanced Arithmetic Architectures and Design Methodologies
Pipelined RLS For VLSI: Star-RLS Filters	519	(32)
K. J. Raghunath
Keshab K. Parhi
Introduction	519	(1)
The QRD-RLS Algorithm	520	(2)
Pipelining Problem in QRD-RLS	522	(2)
Pipelining for Low-Power Designs	524	(1)
Star-RLS Systolic Array Algorithm	525	(4)
Pipelined Star-RLS (PSTAR-RLS) Architecture	529	(6)
Numerical Stability Analysis	535	(1)
Finite-Precision Analysis	536	(5)
A 100 Mhz Pipelined RLS Adaptive Filter	541	(3)
Conclusions	544	(7)
References	544	(7)
Division and Square Root	551	(38)
Hosahalli R. Srinivas
Keshab K. Parhi
Introduction	551	(1)
Division	552	(19)
Square Root	571	(7)
Unified Division Square Root Algorithm	578	(3)
Comparison	581	(8)
References	585	(4)
Finite Field Arithmetic Architecture	589	(34)
Leilei Song
Keshab K. Parhi
Introduction	589	(2)
Mathematical Background	591	(6)
Finite Field Arithmetic Architectures Using Standard Basis	597	(16)
Finite Field Division Algorithms	613	(1)
Finite Field Arithmetic Using Dual Basis Representation	614	(3)
Conclusions	617	(6)
References	619	(4)
CORDIC Algorithms and Architectures	623	(34)
Herbert Dawid
Heinrich Meyr
Introduction	623	(1)
The Cordic Algorithm	624	(9)
Computational Accuracy	633	(4)
Scale Factor Correction	637	(3)
Cordic Architectures	640	(5)
Cordic Architectures Using Redundant Number Systems	645	(12)
References	652	(5)
Advanced Systolic Design	657	(36)
Dominique Lavenier
Patrice Quinton
Sanjay Rajopadhye
Introduction	657	(2)
Systolic Design by Recurrence Transformations	659	(19)
Advanced Systolic Architectures	678	(8)
Conclusion	686	(7)
References	687	(6)
Low Power CMOS VLSI Design	693	(48)
Tadahiro Kuroda
Takayasu Sakurai
Introduction	693	(3)
Analysis Power Dissipation	696	(1)
Low Voltage Circuits	697	(30)
Capacitance Reductance	727	(8)
Summary	735	(6)
References	736	(5)
Power Estimation Approaches	741	(32)
Janardhan H. Satyanarayana
Keshab K. Parhi
Introduction	741	(5)
Previous Work	746	(4)
Theoretical Background	750	(2)
Hierarchical Approach to Power Estimation of Combinatorial Circuits	752	(9)
Power Estimation of Combinatorial Circuits	761	(1)
Experimental Results	762	(7)
Conclusions	769	(4)
References	769	(4)
System Exploration for Custom Low Power Data Storage and Transfer	773	(42)
Francky Catthoor
Sven Wuytack
Eddy De Greef
Florin Balasa
Peter Slock
Introduction	773	(1)
Target Application Domain and Architecture Style	774	(1)
Related Work	775	(2)
Custom Data Transfer and Storage Exploration Methodology	777	(13)
Demonstrator Application for Illustrating the Methodology	790	(12)
Industrial Application Demonstrators for Custom Realizations	802	(3)
Conclusions	805	(10)
References	806	(9)
Hardware Description and Synthesis of DSP Systems	815	(32)
Lori E. Lucke
Junsoo Lee
Introduction	815	(1)
High Level Synthesis	816	(2)
Top Down Design	818	(1)
Design Entry	818	(8)
Functional Simulation	826	(1)
Logic Synthesis	826	(2)
Structural Simulation	828	(2)
Design Analysis	830	(1)
Power Estimation and Low Power Design	831	(5)
Layout	836	(1)
Structural Simulation	837	(1)
Conclusion	837	(2)
Appendix: VHDL Code for 4 Tap FIR Filter	839	(8)
References	843	(4)
Index	847