Fundamentals of Logic Design (with CD-ROM)

by Roth, Jr., Charles H.

• ISBN13: 9780534378042
• ISBN10: 0534378048
• Edition: 5th
• Format: Hardcover
• Copyright: 2003-06-11
• Publisher: CL Engineering

Summary

Updated with modern coverage, a streamlined presentation, and an excellent CD-ROM, this fifth edition achieves a balance between theory and application. Author Charles H. Roth, Jr. carefully presents the theory that is necessary for understanding the fundamental concepts of logic design while not overwhelming students with the mathematics of switching theory. Divided into 20 easy-to-grasp study units, the book covers such fundamental concepts as Boolean algebra, logic gates design, flip-flops, and state machines. By combining flip-flops with networks of logic gates, students will learn to design counters, adders, sequence detectors, and simple digital systems. After covering the basics, this text presents modern design techniques using programmable logic devices and the VHDL hardware description language.

Table of Contents

Preface	xix
How to Use This Book for Self-Study	xxiii
Introduction Number Systems and Conversion	1	(25)
Objectives	1	(1)
Study Guide	2	(4)
Digital Systems and Switching Circuits	6	(2)
Number Systems and Conversion	8	(4)
Binary Arithmetic	12	(3)
Representation of Negative Numbers	15	(5)
Addition of 2's Complement Numbers	17	(1)
Addition of 1's Complement Numbers	18	(2)
Binary Codes	20	(6)
Problems	23	(3)
Boolean Algebra	26	(27)
Objectives	26	(1)
Study Guide	27	(6)
Introduction	33	(1)
Basic Operations	34	(2)
Boolean Expressions and Truth Tables	36	(2)
Basic Theorems	38	(1)
Commutative, Associative, and Distributive Laws	39	(2)
Simplification Theorems	41	(2)
Multiplying Out and Factoring	43	(2)
DeMorgan's Laws	45	(8)
Problems	47	(5)
Laws and Theorems of Boolean Algebra	52	(1)
Boolean Algebra (Continued)	53	(24)
Objectives	53	(1)
Study Guide	54	(4)
Multiplying Out and Factoring Expressions	58	(2)
Exclusive-OR and Equivalence Operations	60	(2)
The Consensus Theorem	62	(2)
Algebraic Simplification of Switching Expressions	64	(2)
Proving the Validity of an Equation	66	(11)
Programmed Exercises	68	(6)
Problems	74	(3)
Applications of Boolean Algebra Minterm and Maxterm Expansions	77	(32)
Objectives	77	(1)
Study Guide	78	(6)
Conversion of English Sentences to Boolean Equations	84	(2)
Combinational Logic Design Using a Truth Table	86	(1)
Minterm and Maxterm Expansions	87	(3)
General Minterm and Maxterm Expansions	90	(3)
Incompletely Specified Functions	93	(1)
Examples of Truth Table Construction	94	(4)
Design of Binary Adders and Subtracters	98	(11)
Problems	101	(8)
Karnaugh Maps	109	(40)
Objectives	109	(1)
Study Guide	110	(10)
Minimum Forms of Switching Functions	120	(1)
Two- and Three-Variable Karnaugh Maps	121	(5)
Four-Variable Karnaugh Maps	126	(3)
Determination of Minimum Expressions Using Essential Prime Implicants	129	(5)
Five-Variable Karnaugh Maps	134	(2)
Other Uses of Karnaugh Maps	136	(2)
Other Forms of Karnaugh Maps	138	(11)
Programmed Exercises	139	(5)
Problems	144	(5)
Quine-McCluskey Method	149	(24)
Objectives	149	(1)
Study Guide	150	(5)
Determination of Prime Implicants	155	(3)
The Prime Implicant Chart	158	(3)
Petrick's Method	161	(1)
Simplification of Incompletely Specified Functions	162	(1)
Simplification Using Map-Entered Variables	163	(2)
Conclusion	165	(8)
Programmed Exercise	166	(4)
Problems	170	(3)
Multi-Level Gate Circuits NAND and NOR Gates	173	(28)
Objectives	173	(1)
Study Guide	174	(5)
Multi-Level Gate Circuits	179	(4)
NAND and NOR Gates	183	(2)
Design of Two-Level Circuits Using NAND and NOR Gates	185	(3)
Design of Multi-Level NAND and NOR Gate Circuits	188	(1)
Circuit Conversion Using Alternative Gate Symbols	189	(3)
Design of Two-Level, Multiple-Output Circuits	192	(4)
Determination of Essential Prime Implicants for Multiple-Output Realization	194	(2)
Multiple-Output NAND and NOR Circuits	196	(5)
Problems	196	(5)
Combinational Circuit Design and Simulation Using Gates	201	(23)
Objectives	201	(1)
Study Guide	202	(3)
Review of Combinational Circuit Design	205	(1)
Design of Circuits with Limited Gate Fan-In	206	(2)
Gate Delays and Timing Diagrams	208	(2)
Hazards in Combinational Logic	210	(3)
Simulation and Testing of Logic Circuits	213	(11)
Problems	216	(2)
Design Problems	218	(6)
Multiplexers, Decoders, and Programmable Logic Devices	224	(33)
Objectives	224	(1)
Study Guide	225	(5)
Introduction	230	(1)
Multiplexers	230	(3)
Three-State Buffers	233	(2)
Decoders and Encoders	235	(3)
Read-Only Memories	238	(4)
Programmable Logic Devices	242	(5)
Programmable Logic Arrays	242	(3)
Programmable Array Logic	245	(2)
Complex Programmable Logic Devices	247	(2)
Field Programmable Gate Arrays	249	(8)
Decomposition of Switching Functions	250	(3)
Problems	253	(4)
Introduction to VHDL	257	(33)
Objectives	257	(1)
Study Guide	258	(4)
VHDL Description of Combinational Circuits	262	(3)
VHDL Models for Multiplexers	265	(2)
VHDL Modules	267	(5)
Four-Bit Full Adder	269	(3)
Signals and Constants	272	(1)
Arrays	273	(3)
VHDL Operators	276	(1)
Packages and Libraries	277	(2)
IEEE Standard Logic	279	(3)
Compilation and Simulation of VHDL Code	282	(8)
Problems	283	(7)
Latches and Flip-Flops	290	(29)
Objectives	290	(1)
Study Guide	291	(4)
Introduction	295	(1)
Set-Reset Latch	296	(4)
Gated D Latch	300	(1)
Edge-Triggered D Flip-Flop	301	(2)
S-R Flip-Flop	303	(2)
J-K Flip-Flop	305	(1)
T Flip-Flop	306	(1)
Flip-Flops with Additional Inputs	307	(2)
Summary	309	(10)
Problems	310	(6)
Programmed Exercise	316	(3)
Registers and Counters	319	(36)
Objectives	319	(1)
Study Guide	320	(5)
Registers and Register Transfers	325	(4)
Parallel Adder with Accumulator	327	(2)
Shift Registers	329	(4)
Design of Binary Counters	333	(5)
Counters for Other Sequences	338	(4)
Counter Design Using D Flip-Flops	341	(1)
Counter Design Using S-R and J-K Flip-Flops	342	(3)
Derivation of Flip-Flop Input Equations---Summary	345	(10)
Problems	349	(6)
Analysis of Clocked Sequential Circuits	355	(35)
Objectives	355	(1)
Study Guide	356	(6)
A Sequential Parity Checker	362	(2)
Analysis by Signal Tracing and Timing Charts	364	(3)
State Tables and Graphs	367	(7)
Construction and Interpretation of Timing Charts	372	(2)
General Models for Sequential Circuits	374	(16)
Programmed Exercise	378	(4)
Problems	382	(8)
Derivation of State Graphs and Tables	390	(35)
Objectives	390	(1)
Study Guide	391	(2)
Design of a Sequence Detector	393	(5)
More Complex Design Problems	398	(4)
Guidelines for Construction of State Graphs	402	(5)
Serial Data Code Conversion	407	(3)
Alphanumeric State Graph Notation	410	(15)
Programmed Exercises	412	(7)
Problems	419	(6)
Reduction of State Tables State Assignment	425	(40)
Objectives	425	(1)
Study Guide	426	(7)
Elimination of Redundant States	433	(1)
Equivalent States	434	(3)
Determination of State Equivalence Using an Implication Table	437	(3)
Equivalent Sequential Circuits	440	(2)
Incompletely Specified State Tables	442	(1)
Derivation of Flip-Flop Input Equations	443	(3)
Equivalent State Assignments	446	(3)
Guidelines for State Assignment	449	(4)
Using a One-Hot State Assignment	453	(12)
Problems	455	(10)
Sequential Circuit Design	465	(36)
Objectives	465	(1)
Study Guide	466	(2)
Summary of Design Procedure for Sequential Circuits	468	(1)
Design Example---Code Converter	469	(3)
Design of Iterative Circuits	472	(4)
Design of a Comparator	473	(3)
Design of Sequential Circuits Using ROMs and PLAs	476	(3)
Sequential Circuit Design Using CPLDs	479	(4)
Sequential Circuit Design Using FPGAs	483	(2)
Simulation and Testing of Sequential Circuits	485	(5)
Overview of Computer-Aided Design	490	(11)
Design Problems	492	(6)
Additional Problems	498	(3)
VHDL for Sequential Logic	501	(34)
Objectives	501	(1)
Study Guide	502	(4)
Modeling Flip-Flops Using VHDL Processes	506	(3)
Modeling Registers and Counters Using VHDL Processes	509	(5)
Modeling Combinational Logic Using VHDL Processes	514	(1)
Modeling a Sequential Machine	515	(7)
Synthesis of VHDL Code	522	(3)
More about Processes and Sequential Statements	525	(10)
Problems	527	(6)
Simulation Problems	533	(2)
Circuits for Arithmetic Operations	535	(28)
Objectives	535	(1)
Study Guide	536	(2)
Serial Adder with Accumulator	538	(4)
Design of a Parallel Multiplier	542	(4)
Design of a Binary Divider	546	(17)
Programmed Exercises	551	(4)
Problems	555	(8)
State Machine Design with SM Charts	563	(20)
Objectives	563	(1)
Study Guide	564	(1)
State Machine Charts	565	(4)
Derivation of SM Charts	569	(6)
Realization of SM Charts	575	(8)
Problems	579	(4)
VHDL for Digital System Design	583	(27)
Objectives	583	(1)
Study Guide	584	(3)
VHDL Code for a Serial Adder	587	(1)
VHDL Code for a Binary Multiplier	588	(11)
VHDL Code for a Binary Divider	599	(2)
VHDL Code for a Dice Game Simulator	601	(3)
Concluding Remarks	604	(6)
Problems	605	(3)
Lab Design Problems	608	(2)
A Appendices	610	(13)
A MOS and CMOS Logic	610	(6)
B VHDL Language Summary	616	(5)
C Proofs of Theorems	621	(2)
References	623	(1)
Answers to Selected Study Guide Questions and Problems	624	(57)
Index	681