High Performance Embedded Architectures and Compilers : Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings

by Stenstrom, Per; Dubois, Michel; Katevenis, Manolis; Gupta, Rajiv; Ungerer, Theo

• ISBN13: 9783540775591
• ISBN10: 3540775595
• Format: Paperback
• Copyright: 2008-03-21
• Publisher: Springer Verlag

Summary

This book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008.The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized in topical sections on Multithreaded and Multicore Processors, Reconfigurable - ASIP, Compiler Optimizations, Industrial Processors and Application Parallelization, Power-Aware Techniques, High-Performance Processors, Profiles: Collection and Analysis as well as Optimizing Memory Performance.

Table of Contents

Supercomputing for the Future, Supercomputing from the Past (Keynote)	p. 3
Multithreaded and Multicore Processors
MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing	p. 9
rMPI: Message Passing on Multicore Processors with On-Chip Interconnect	p. 22
Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE	p. 38
Reconfigurable - ASIP
BRAM-LUT Tradeoff on a Polymorphic DES Design	p. 55
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array	p. 66
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP	p. 82
Compiler Optimizations
Fast Bounds Checking Using Debug Register	p. 99
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis	p. 114
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems	p. 130
Industrial Processors and Application Parallelization
Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions	p. 147
Experiences with Parallelizing a Bio-informatics Program on the Cell BE	p. 161
Drug Design Issues on the Cell BE	p. 170
Power-Aware Techniques
Coffee: COmpiler Framework for Energy-Aware Exploration	p. 193
Integrated CPU Cache Power Management in Multiple Clock Domain Processors	p. 209
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation	p. 224
High-Performance Processors
The Significance of Affectors and Affectees Correlations for Branch Prediction	p. 243
Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator	p. 258
LPA: A First Approach to the Loop Processor Architecture	p. 273
Profiles: Collection and Analysis
Complementing Missing and Inaccurate Profiling Using a Minimum Coat Circulation Algorithm	p. 291
Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy	p. 305
Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior	p. 320
Optimizing Memory Performance
MLP-Aware Dynamic Cache Partitioning	p. 337
Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture	p. 353
Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory	p. 369
Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache	p. 384
Author Index	p. 399
Table of Contents provided by Blackwell. All Rights Reserved.