Introduction to Logic Design, Second Edition

by Shiva; Sajjan G.

• ISBN13: 9780824700829
• ISBN10: 0824700821
• Edition: 2nd
• Format: Hardcover
• Copyright: 1998-01-20
• Publisher: CRC Press

Summary

The second edition of this text provides an introduction to the analysis and design of digital circuits at a logic, instead of electronics, level. It covers a range of topics, from number system theory to asynchronous logic design. A solution manual is available to instructors only. Requests must be made on official school stationery.

Table of Contents

Preface	v
1 Number Systems and Codes	1	(51)
1.1 Digital System Organization	1	(2)
1.2 Number Systems	3	(5)
1.2.1 Binary System	5	(1)
1.2.2 Octal System	6	(1)
1.2.3 Hexadecimal System	7	(1)
1.3 Conversion	8	(6)
1.3.1 Radix Division Technique	8	(1)
1.3.2 Radix Multiply Technique	9	(3)
1.3.3 Base 2^k Conversion	12	(2)
1.4 Arithmetic	14	(11)
1.4.1 Binary Arithmetic	14	(5)
1.4.2 Octal Arithmetic	19	(2)
1.4.3 Hexadecimal Arithmetic	21	(4)
1.5 Representation of Negative Numbers	25	(10)
1.5.1 Sign-Magnitude System	25	(1)
1.5.2 Complement Number System	26	(6)
1.5.3 Shifting Revisited	32	(2)
1.5.4 Comparison of Complement Systems	34	(1)
1.6 Floating-Point Numbers	35	(3)
1.7 Binary Codes	38	(6)
1.7.1 Weighted Codes	39	(2)
1.7.2 Nonweighted Codes	41	(1)
1.7.3 Error Detection Codes	42	(1)
1.7.4 Alphanumeric Codes	43	(1)
1.8 Data Storage and Register Transfer	44	(4)
1.9 Summary	48	(1)
References	48	(1)
Problems	48	(4)
2 Boolean Algebra	52	(48)
2.1 Logic Circuits	52	(5)
2.1.1 Signals and Gates	55	(2)
2.2 Boolean Algebra	57	(1)
2.3 Two-Valued Boolean Algebra	58	(2)
2.4 Properties of Boolean Algebra	60	(1)
2.4.1 Operator Hierarchy	60	(1)
2.4.2 Equality of Expressions	60	(1)
2.4.3 Duality	60	(1)
2.5 Functions and Their Representations	61	(10)
2.5.1 Truth Tables	61	(1)
2.5.2 Venn Diagrams	62	(1)
2.5.3 Algebraic Representations	63	(8)
2.6 Theorems	71	(11)
2.6.1 Expansion to Canonical Forms	76	(3)
2.6.2 Proving the Equality of Expressions	79	(1)
2.6.3 Simplifying Boolean Functions	80	(2)
2.7 Other Operations	82	(3)
2.7.1 A Functionally Complete Set of Operators	84	(1)
2.8 Multiple-Input Gates and Logic Circuits	85	(3)
2.9 Integrated Circuits	88	(7)
2.9.1 Positive and Negative Logic	91	(2)
2.9.2 Signal Inversion	93	(2)
2.10 Current Trends	95	(1)
2.10.1 Multivalued Logic	95	(1)
2.10.2 Fuzzy Logic	96	(1)
2.11 Summary	96	(1)
References	97	(1)
Problems	97	(3)
3 Minimization of Boolean Functions	100	(38)
3.1 K-maps	101	(16)
3.1.1 Representation of Functions on K-maps	105	(1)
3.1.2 Plotting the SOP Form	106	(2)
3.1.3 Plotting the POS Form	108	(2)
3.1.4 Minimization	110	(7)
3.2 Incompletely Specified Functions	117	(4)
3.3 Quine-McCluskey Procedure	121	(13)
3.3.1 Covering Problem	128	(4)
3.3.2 Multiple-Output Functions	132	(2)
3.4 CAD Tools for Simplification	134	(1)
3.5 Summary	135	(1)
References	135	(1)
Problems	136	(2)
4 Combinational Circuits	138	(49)
4.1 Introduction	138	(1)
4.2 Functional Analysis	139	(3)
4.3 Design	142	(13)
4.3.1 AND-OR Circuits	143	(1)
4.3.2 OR-AND Circuits	144	(1)
4.3.3 NAND-NAND Circuits	145	(1)
4.3.4 NOR-NOR Circuits	145	(10)
4.4 Other Two-Level Circuits	155	(4)
4.5 EXCLUSIVE-OR and EQUIVALENCE	159	(6)
4.6 Multiple-Level Circuits Revisited	165	(2)
4.7 Timing Analysis	167	(5)
4.7.1 Hazards	169	(3)
4.8 Loading Analysis	172	(1)
4.9 Designing with ICs	173	(10)
4.9.1 Special ICs	176	(7)
4.10 Summary	183	(1)
References	183	(1)
Problems	183	(4)
5 Popular Combinational Circuits	187	(56)
5.1 Introduction	187	(2)
5.2 Adders	189	(12)
5.2.1 Parallel Binary Adder (PBA)	189	(3)
5.2.2 Carry Lookahead Adder (CLA)	192	(3)
5.2.3 Off-the-Shelf Adders	195	(2)
5.2.4 Decimal Adder	197	(4)
5.3 Magnitude Comparators	201	(1)
5.4 Shifters	201	(2)
5.5 Arithmetic/Logic Units (ALUs)	203	(4)
5.6 Multipliers	207	(5)
5.7 Decoders	212	(7)
5.8 Code Converters	219	(2)
5.9 Encoders	221	(2)
5.10 Multiplexers	223	(5)
5.11 Demultiplexers	228	(6)
5.12 Majority Circuits	234	(3)
5.13 Modular Design Methodology	237	(3)
5.14 Summary	240	(1)
References	240	(1)
Problems	241	(2)
6 Synchronous Sequential Circuits	243	(77)
6.1 Introduction	243	(3)
6.2 Flip-Flops	246	(9)
6.2.1 Set-Reset (SR) Flip-Flops	247	(3)
6.2.2 D Flip-Flops	250	(1)
6.2.3 JK Flip-Flops	251	(1)
6.2.4 T Flip-Flops	252	(1)
6.2.5 Characteristic and Excitation Tables	253	(2)
6.3 Timing Characteristics of Flip-Flops	255	(6)
6.3.1 Master-Slave Flip-Flops	256	(2)
6.3.2 Edge-Triggered Flip-Flops	258	(3)
6.4 Flip-Flop ICs	261	(3)
6.5 Analysis of Synchronous Sequential Circuits	264	(12)
6.6 Mealy and Moore Models	276	(3)
6.7 Design of Synchronous Sequential Circuits	279	(11)
6.7.1 Circuit Minimization	285	(5)
6.8 State Reduction	290	(5)
6.8.1 Equivalence Partitioning	291	(2)
6.8.2 Implication Charts	293	(2)
6.9 State Assignment	295	(8)
6.10 Incompletely Specified Sequential Circuits	303	(9)
6.10.1 State Reduction Procedure	308	(4)
6.11 Summary	312	(1)
References	313	(1)
Problems	314	(6)
7 Popular Sequential Circuits	320	(72)
7.1 Introduction	320	(1)
7.2 Registers	321	(5)
7.3 Latches	326	(1)
7.4 Shift Registers	327	(12)
7.4.1 Static Shift Registers	327	(8)
7.4.2 Dynamic Shift Registers	335	(4)
7.5 Register Transfer Logic	339	(10)
7.5.1 Register Transfer Schemes	342	(1)
7.5.2 Register Transfer Languages	343	(6)
7.6 Register Files	349	(3)
7.7 Counters	352	(20)
7.7.1 Design of Synchronous Counters	355	(4)
7.7.2 Design of Ripple Counters	359	(4)
7.7.3 Divide-by-N Circuits	363	(3)
7.7.4 IC Counters	366	(6)
7.8 Designing with ICs	372	(7)
7.8.1 Generation of Timing Signals	373	(3)
7.8.2 Clock Skewing	376	(3)
7.9 Design of Control Circuits	379	(9)
7.9.1 ASM Charts	386	(2)
7.10 Summary	388	(1)
References	389	(1)
Problems	389	(3)
8 Asynchronous Circuits	392	(58)
8.1 Introduction	392	(3)
8.2 Pulse-Mode Circuits	395	(6)
8.3 Fundamental-Mode Circuits	401	(17)
8.3.1 Analysis	401	(7)
8.3.2 Design	408	(10)
8.4 Effects of Component Delays	418	(4)
8.4.1 Hazards	418	(1)
8.4.2 Cycles and Races	419	(3)
8.5 State Assignment	422	(9)
8.5.1 Shared-Row Method	423	(3)
8.5.2 Multiple-Row Method	426	(2)
8.5.3 One-Hot Method	428	(3)
8.6 Generation of Timing Signals	431	(7)
8.7 Switch Bouncing	438	(4)
8.8 A Power-on Reset Circuit	442	(1)
8.9 Summary	443	(1)
References	443	(1)
Problems	443	(7)
9 Programmable Logic	450	(44)
9.1 Introduction	450	(1)
9.2 IC Fabrication	451	(2)
9.3 Circuit Implementation Modes and Devices	453	(3)
9.4 Read Only Memory	456	(10)
9.4.1 Types of ROMs	460	(1)
9.4.2 Off-the-Shelf ROMs	461	(1)
9.4.3 Multiple-Module Implementations	461	(5)
9.5 Programmable Logic Arrays (PLAs)	466	(6)
9.5.1 Types of PLAs	468	(3)
9.5.2 Off-the-Shelf PLAs	471	(1)
9.6 Programmable Array Logic (PAL)	472	(11)
9.6.1 Types of PALs	480	(1)
9.6.2 Off-the-Shelf PALs	481	(2)
9.7 Gate Arrays (GA)	483	(8)
9.7.1 Off-the-Shelf GAs	486	(5)
9.8 Summary	491	(1)
References	492	(1)
Problems	493	(1)
10 Hardware Technologies	494	(48)
10.1 Introduction	494	(1)
10.2 Bipolar IC Technologies	495	(25)
10.2.1 Diode Logic Gates	495	(3)
10.2.2 Transistor Logic Gates	498	(4)
10.2.3 RTL Gates	502	(1)
10.2.4 DTL Gates	503	(2)
10.2.5 TTL Logic	505	(12)
10.2.6 ECL Gates	517	(3)
10.3 Metal Oxide Semiconductor (MOS) IC Technology	520	(9)
10.3.1 NMOS Logic Gates	521	(5)
10.3.2 CMOS Logic	526	(3)
10.4 Gallium Arsenide IC Technology	529	(4)
10.5 Optical Technology	533	(5)
10.6 Summary	538	(1)
References	539	(1)
Problems	539	(3)
11 Laboratory Experiments	542	(14)
References	555	(1)
APPENDIX A IEEE Standard Logic Symbols	556	(12)
A.1 Introduction	556	(1)
A.2 Representation of SSI Functions	557	(6)
A.3 Representation of MSI Functions	563	(3)
A.4 Dependency	566	(1)
References	567	(1)
APPENDIX B Fundamentals of Electrical Circuits	568	(7)
References	574	(1)
APPENDIX C Simulation	575	(6)
References	579	(2)
APPENDIX D CAD Tools for Designing with PLDs and FPGAs	581	(32)
D.1 Warp2+	581	(1)
D.2 VHDL	582	(1)
D.3 Designing with Warp2+	583	(6)
D.4 Designing with PLAs	589	(5)
D.5 AMAZE System	594	(3)
D.6 Designing with PALs	597	(14)
References	611	(2)
Index	613