Rapid Prototyping of Digital Systems: Sopc Edition,9780387726700

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Rapid Prototyping of Digital Systems: Sopc Edition

by Hamblen, James O.; Hall, Tyson S.; Furman, Michael D.

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ISBN13:

9780387726700

ISBN10:

0387726705

Format:

Paperback

Pub. Date:

1/30/2008

Publisher(s):

Springer Verlag

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Summary

This book provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and excercises are also appropriate for an upper level course in digital logic or embedded systems. The goal of this text is to introduce fully integrated modern CAD tools, logic simulation, logic synthesis using hardware description languages, design hierarchy, current generation field programmable gate array (FPGA) technology, and SOPC design in the laboratory portion of the course. Even student laboratory projects can now implement entire digital and computer systems with hundreds of thousands of gates. The book includes a number of interesting and challenging laboratory projects involving serial communications, state machines with video output, video games and graphics, simple computers, keyboard and mouse interfaces, robotics, pipelined RISC processor cores, designing a computer system using a commercial processor core, C programs running on processor cores, and porting Linux to the board. Source files and additional example files are available on the CD-ROM for all designs presented in the text. The student version of the PC based CAD tool on the CD-ROM can be freely distributed to students.

Tutorial I: The 15 Minute Design	p. 2
Design Entry using the Graphic Editor	p. 9
Compiling the Design	p. 16
Simulation of the Design	p. 17
Testing Your Design on an FPGA Board	p. 18
Downloading Your Design to the DE1 Board	p. 19
Downloading Your Design to the DE2 Board	p. 22
Downloading Your Design to the UP3 Board	p. 25
Downloading Your Design to the UP2 or UP1 Board	p. 27
The 10 Minute VHDL Entry Tutorial	p. 29
Compiling the VHDL Design	p. 32
The 10 Minute Verilog Entry Tutorial	p. 34
Compiling the Verilog Design	p. 36
Timing Analysis	p. 38
The Floorplan Editor	p. 39
Symbols and Hierarchy	p. 40
Functional Simulation	p. 41
Laboratory Exercises	p. 42
	p. 46
FPGA and External Hardware Features	p. 47
The FPGA Board's Memory Features	p. 48
The FPGA Board's I/O Features	p. 49
Obtaining an FPGA Development Board and Cables	p. 53
Programmable Logic Technology	p. 56
CPLDs and FPGAs	p. 59
Altera MAX 7000S Architecture - A Product Term CPLD Device	p. 60
Altera Cyclone Architecture - A Look-Up Table FPGA Device	p. 62
Xilinx 4000 Architecture - A Look-Up Table FPGA Device	p. 65
Computer Aided Design Tools for Programmable Logic	p. 67
Next Generation FPGA CAD tools	p. 68
Applications of FPGAs	p. 69
Features of New Generation FPGAs	p. 69
For additional information	p. 70
Laboratory Exercises	p. 71
Tutorial II: Sequential Design and Hierarchy	p. 74
Install the Tutorial Files and FPGAcore Library for your board	p. 74
Open the tutor2 Schematic	p. 75
Browse the Hierarchy	p. 76
Using Buses in a Schematic	p. 78
Testing the Pushbutton Counter and Displays	p. 79
Testing the Initial Design on the Board	p. 80
Fixing the Switch Contact Bounce Problem	p. 81
Testing the Modified Design on the FPGA Board	p. 82
Laboratory Exercises	p. 83
FPGAcore Library Functions	p. 88
FPGAcore LCD_Display: LCD Panel Character Display	p. 90
FPGAcore DEC_7SEG: Hex to Seven-segment Decoder	p. 92
FPGAcore Debounce: Pushbutton Debounce	p. 94
FPGAcore OnePulse: Pushbutton Single Pulse	p. 95
FPGAcore Clk_Div: Clock Divider	p. 96
FPGAcore VGA_Sync: VGA Video Sync Generation	p. 97
FPGAcore Char_ROM: Character Generation ROM	p. 99
FPGAcore Keyboard: Read Keyboard Scan Code	p. 100
FPGAcore Mouse: Mouse Cursor	p. 102
For additional information	p. 103
Using VHDL for Synthesis of Digital Hardware	p. 106
VHDL Data Types	p. 106
VHDL Operators	p. 107
VHDL Based Synthesis of Digital Hardware	p. 108
VHDL Synthesis Models of Gate Networks	p. 108
VHDL Synthesis Model of a Seven-segment LED Decoder	p. 109
VHDL Synthesis Model of a Multiplexer	p. 111
VHDL Synthesis Model of Tri-State Output	p. 112
VHDL Synthesis Models of Flip-flops and Registers	p. 112
Accidental Synthesis of Inferred Latches	p. 114
VHDL Synthesis Model of a Counter	p. 114
VHDL Synthesis Model of a State Machine	p. 115
VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter	p. 117
VHDL Synthesis of Multiply and Divide Hardware	p. 118
VHDL Synthesis Models for Memory	p. 119
Hierarchy in VHDL Synthesis Models	p. 123
Using a Testbench for Verification	p. 125
For additional information	p. 126
Laboratory Exercises	p. 126
Using Verilog for Synthesis of Digital Hardware	p. 130
Verilog Data Types	p. 130
Verilog Based Synthesis of Digital Hardware	p. 130
Verilog Operators	p. 131
Verilog Synthesis Models of Gate Networks	p. 132
Verilog Synthesis Model of a Seven-segment LED Decoder	p. 132
Verilog Synthesis Model of a Multiplexer	p. 133
Verilog Synthesis Model of Tri-State Output	p. 134
Verilog Synthesis Models of Flip-flops and Registers	p. 135
Accidental Synthesis of Inferred Latches	p. 136
Verilog Synthesis Model of a Counter	p. 136
Verilog Synthesis Model of a State Machine	p. 137
Verilog Synthesis Model of an ALU with an Adder/Subtractor and a Shifter	p. 138
Verilog Synthesis of Multiply and Divide Hardware	p. 139
Verilog Synthesis Models for Memory	p. 140
Hierarchy in Verilog Synthesis Models	p. 143
For additional information	p. 144
Laboratory Exercises	p. 144
State Machine Design: The Electric Train Controller	p. 148
The Train Control Problem	p. 148
Train Direction Outputs (DA1-DA0, and DB1-DB0)	p. 149
Switch Direction Outputs (SW1, SW2, and SW3)	p. 150
Train Sensor Input Signals (S1, S2, S3, S4, and S5)	p. 150
An Example Controller Design	p. 151
VHDL Based Example Controller Design	p. 154
Verilog Based Example Controller Design	p. 157
Automatically Generating a State Diagram of a Design	p. 160
Simulation Vector file for State Machine Simulation	p. 161
Running the Train Control Simulation	p. 162
Running the Video Train System (After Successful Simulation)	p. 162
A Hardware Implementation of the Train System Layout	p. 164
Laboratory Exercises	p. 166
A Simple Computer Design: The ¿P 3	p. 170
Computer Programs and Instructions	p. 171
The Processor Fetch, Decode and Execute Cycle	p. 172
VHDL Model of the ¿P 3	p. 179
Verilog Model of the ¿P 3	p. 182
Automatically Generating a State Diagram of the ¿P3	p. 186
Simulation of the ¿P3 Computer	p. 187
Laboratory Exercises	p. 188
	p. 192
Video Display Technology	p. 192
Video Refresh	p. 192
Using an FPGA for VGA Video Signal Generation	p. 195
A VHDL Sync Generation Example: FPGAcore VGA_SYNC	p. 196
Final Output Register for Video Signals	p. 198
Required Pin Assignments for Video Output	p. 198
Video Examples	p. 199
A Character Based Video Design	p. 200
Character Selection and Fonts	p. 200
VHDL Character Display Design Examples	p. 203
A Graphics Memory Design Example	p. 206
Video Data Compression	p. 207
Video Color Mixing using Dithering	p. 207
VHDL Graphics Display Design Example	p. 208
Higher Video Resolution and Faster Refresh Rates	p. 209
Laboratory Exercises	p. 210
Interfacing to the PS/2 Keyboard and Mouse	p. 214
PS/2 Port Connections	p. 214
Keyboard Scan Codes	p. 215
Make and Break Codes	p. 215
The PS/2 Serial Data Transmission Protocol	p. 216
Scan Code Set 2 for the PS/2 Keyboard	p. 218
The Keyboard FPGAcore	p. 220
A Design Example Using the Keyboard FPGAcore	p. 223
Interfacing to the PS/2 Mouse	p. 224
The Mouse FPGAcore	p. 226
Mouse Initialization	p. 226
Mouse Data Packet Processing	p. 227
An Example Design Using the Mouse FPGAcore	p. 228
For Additional Information	p. 229
Laboratory Exercises	p. 229
Legacy Digital I/O Interfacing Standards	p. 232
Parallel I/O Interface	p. 232
RS-232C Serial I/O Interface	p. 233
SPI Bus Interface	p. 235
I²C Bus Interface	p. 237
For Additional Information	p. 239
Laboratory Exercises	p. 239
FPGA Robotics Projects	p. 242
The FPGA-bot Design	p. 242
FPGA-bot Servo Drive Motors	p. 242
Modifying the Servos to make Drive Motors	p. 243
VHDL Servo Driver Code for the FPGA-bot	p. 244
Low-cost Sensors for an FPGA Robot Project	p. 246
Assembly of the FPGA-bot Body	p. 259
I/O Connections to the board's Expansion Headers	p. 266
Robot Projects Based on R/C Toys, Models, and Robot Kits	p. 267
For Additional Information	p. 275
Laboratory Exercises	p. 277
	p. 284
The MIPS Instruction Set and Processor	p. 284
Using VHDL to Synthesize the MIPS Processor Core	p. 287
The Top-Level Module	p. 288
The Control Unit	p. 291
The Instruction Fetch Stage	p. 293
The Decode Stage	p. 296
The Execute Stage	p. 298
The Data Memory Stage	p. 300
Simulation of the MIPS Design	p. 301
MIPS Hardware Implementation on the FPGA Board	p. 302
For Additional Information	p. 303
Laboratory Exercises	p. 304
Introducing System-on-a-Programmable-Chip	p. 310
Processor Cores	p. 310
SOPC Design Flow	p. 311
Initializing Memory	p. 313
SOPC Design versus Traditional Design Modalities	p. 315
An Example SOPC Design	p. 316
Hardware/Software Design Alternatives	p. 317
For additional information	p. 317
Laboratory Exercises	p. 318
Tutorial III: Nios II Processor Software Development	p. 322
Install the DE board files	p. 322
Starting a Nios II Software Project	p. 322
The Nios II IDE Software	p. 324
Generating the Nios II System Library	p. 325
Software Design with Nios II Peripherals	p. 326
Starting Software Design - main()	p. 329
Downloading the Nios II Hardware and Software Projects	p. 330
Executing the Software	p. 331
Starting Software Design for a Peripheral Test Program	p. 331
Handling Interrupts	p. 334
Accessing Parallel I/O Peripherals	p. 335
Communicating with the LCD Display (DE2 only)	p. 336
Testing SRAM	p. 339
Testing Flash Memory	p. 340
Testing SDRAM	p. 341
Downloading the Nios II Hardware and Software Projects	p. 346
Executing the Software	p. 347
For additional information	p. 347
Laboratory Exercises	p. 348
Tutorial IV: Nios II Processor Hardware Design	p. 352
Install the DE board files	p. 352
Creating a New Project	p. 352
Starting SOPC Builder	p. 353
Adding a Nios II Processor	p. 355
Adding UART Peripherals	p. 358
Adding an Interval Timer Peripheral	p. 359
Adding Parallel I/O Components	p. 360
Adding an SRAM Memory Controller	p. 361
Adding an SDRAM Memory Controller	p. 362
Adding the LCD Module (DE2 Board Only)	p. 362
Adding an External Bus	p. 363
Adding Components to the External Bus	p. 364
Global Processor Settings	p. 364
Finalizing the Nios II Processor	p. 365
Add the Processor Symbol to the Top-Level Schematic	p. 366
Create a Phase-Locked Loop Component	p. 367
Complete the Top-Level Schematic	p. 368
Design Compilation	p. 368
Testing the Nios II Project	p. 369
For additional information	p. 370
Laboratory Exercises	p. 370
Operating System Support for SOPC Design	p. 374
Nios II OS Support	p. 376
eCos	p. 377
¿C/OS-II	p. 378
¿Clinux	p. 379
Implementing the ¿Clinux on the DE Board	p. 380
Hardware Design for ¿Clinux Support	p. 380
Configuring the DE Board	p. 382
Exploring ¿Clinux on the DE Board	p. 385
PS/2 Device Support in ¿Clinux	p. 386
Video Display in ¿Clinux	p. 386
USB Devices in ¿Clinux (DE2 Board Only)	p. 387
Network Communication in ¿Clinux (DE2 Board Only)	p. 387
For additional information	p. 388
Laboratory Exercises	p. 388
Generation of Pseudo Random Binary Sequences	p. 391
Quartus II Design and Data File Extensions	p. 393
Common FPGA Pin Assignments	p. 394
ASCII Character Code	p. 396
Common I/O Connector Pin Assignments	p. 397
Glossary	p. 399
Index	p. 407
About the Accompanying DVD	p. 411
Table of Contents provided by Publisher. All Rights Reserved.