Transactions on High-Performance Embedded Architectures and Compilers II

by Stenstrom, Per

• ISBN13: 9783642009037
• ISBN10: 3642009034
• Format: Paperback
• Copyright: 2009-04-30
• Publisher: Springer-Verlag New York Inc

Summary

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.

Table of Contents

Special Section on High-Performance Embedded Architectures and Compilers
Introduction	p. 3
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches	p. 4
Compiler-Assisted Memory Encryption for Embedded Processors	p. 23
Branch Predictor Warmup for Sampled Simulation through Branch History Matching	p. 45
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems	p. 65
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization	p. 85
Regular Papers
Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors	p. 107
Fetch Gating Control through Speculative Instruction Window Weighting	p. 128
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers	p. 149
Linux Kernel Compaction through Cold Code Swapping	p. 173
Complexity Effective Bypass Networks	p. 201
A Context-Parameterized Model for Static Analysis of Execution Times	p. 222
Reexecution and Selective Reuse in Checkpoint Processors	p. 242
Compiler Support for Code Size Reduction Using a Queue-Based Processor	p. 269
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC	p. 286
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories	p. 307
Author Index	p. 327
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