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9780387328638

Digital Phase Lock Loops

by ; ;
  • ISBN13:

    9780387328638

  • ISBN10:

    0387328637

  • Format: Hardcover
  • Copyright: 2006-12-15
  • Publisher: Springer Verlag
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Summary

Digital phase lock loops are critical components of many communication, signal processing and control systems. This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops then illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity. The practical real-time results, of the various TDTL architectures, obtained from the reconfigurable implementations are compared with those obtained through simulations with MATLAB/Simulink. The material in this book will be valuable to researchers, graduate students, and practicing engineers.

Author Biography

Prof. Al-Araji received the B.Sc., M.Sc., and Ph.D. degrees from the University of Wales Swansea, (UK), all in electrical engineering in 1968, 1969, and 1972 respectively. Since September 2002, Professor Al-Araji was appointed Professor and Head of Communications Engineering Department at Etisalat University College (Emirates Telecommunication Cooperation), Sharjah, UAE. Prior to that and for six years he was working at the Transmission Network Systems, Scientific-Atlanta, Atlanta, Georgia, USA as Senior Staff Electrical Engineer. During the academic year 1995/1996, Prof. Al-Araji was visiting professor at the Ohio State University, Columbus, Ohio, USA. He was visiting professor at King's College, University of London, England, during the summers of 1988 and 1989. Prof. Al-Araji was professor and Department Head at the University of Baghdad, Iraq, and the University of Yarmouk, Jordan. Prof. Al-Araji was awarded the British IERE Clerk Maxwell Premium for a paper published in 1976 and the Scientific-Atlanta award for outstanding achievement in the year 2000. He was an Iraqi National member of URSI Commissions C and D, and the ITU (CCIR Group 8). His research interests include synchronization techniques, communication signal processing, and CATV systems and networks. He has published over 50 papers in international Journals and Conferences and holds 6 US Patents and one International Patent. He is a reviewer to a number of international conferences and journals, and is involved in the organization of a number of international conferences in various capacities. Prof. Al-Araji is a senior member of the IEEE. His e-mail address is: alarajis@euc.ac.ae.

Table of Contents

Preface xi
Acknowledgement xv
Acronyms xvii
1 General Review of Phase-Locked Loops 1(14)
1.1 Overview of Phase-Locked Synchronization Schemes
1(2)
1.2 The Synchronization Challenge
3(1)
1.3 Phase-Locked Loops
4(9)
1.3.1 Analog Phase-locked Loops
4(2)
1.3.2 PLL Basic Components
6(4)
1.3.3 PLL analysis
10(3)
1.4 Conclusions
13(2)
2 Digital Phase Lock Loops 15(16)
2.1 Introduction
15(1)
2.2 Classification of DPLLs
16(14)
2.3 Conclusions
30(1)
3 The Time-Delay Digital Tanlock Loops (TDTLs) 31(20)
3.1 Introduction
31(1)
3.2 Structure and System Equation
32(3)
3.2.1 Structure of the TDTL
32(1)
3.2.2 System Equation
32(2)
3.2.3 The Characteristic Function
34(1)
3.3 System Analysis
35(10)
3.3.1 First-order TDTL
35(8)
3.3.2 Second-Order TDTL
43(2)
3.4 Locking Speed
45(3)
3.4.1 Convergence of the First-Order TDTL
46(2)
3.5 Conclusions
48(3)
4 Hilbert Transformer and Time-Delay 51(18)
4.1 Introduction
51(2)
4.2 Statistical Behavior of HT and Time-Delay in i.i.d. Additive Gaussian Noise
53(13)
4.2.1 Input-Output Relationships in the Presence of Noise
53(1)
4.2.2 Joint PDF of the Amplitude and Phase Random Variables
54(2)
4.2.3 PDF of the Phase Random Variable
56(1)
4.2.4 PDF of the Phase Noise
57(1)
4.2.5 Expectation and Variance of the Phase Noise
58(4)
4.2.6 The phase Estimator and Ranges of Cramer-Rao Bounds
62(3)
4.2.7 A Symmetric Transformation
65(1)
4.3 Conclusions
66(3)
5 The Time-delay Digital Tanlock Loop in Noise 69(16)
5.1 Introduction
69(1)
5.2 Noise Analysis of the TDTL
70(11)
5.2.1 System Equation
70(1)
5.2.2 Statistical Behavior of TDTL Phase Error Detector
71(3)
5.2.3 Phase Estimation and Cramer-Rao Bounds
74(3)
5.2.4 Statistical Behavior of the TDTL in Gaussian Noise
77(4)
5.3 Conclusions
81(4)
6 Architectures for Improved Performance 85(52)
6.1 Introduction
85(1)
6.2 Simulation Results of First-Order TDTL
85(3)
6.3 Improved First-Order TDTL Architectures
88(27)
6.3.1 Delay Switching Architecture
89(5)
6.3.2 Adaptive Gain Architecture
94(6)
6.3.3 Combined Delay Switching and Adaptive Gain
100(5)
6.3.4 Sample Sensing Adaptive Architecture
105(8)
6.3.5 Early Error Sensing Adaptive Architecture
113(2)
6.4 Simulation Results of Second-Order TDTL
115(6)
6.5 Improved Second-Order TDTL Architectures
121(2)
6.5.1 Adaptive Filter Coefficients Second-Order TDTL
121(2)
6.5.2 Adaptive Loop Gain Second-Order TDTL
123(1)
6.6 A Variable Order TDTL Architecture
123(11)
6.7 Conclusions
134(3)
7 FPGA Reconfigurable TDTL 137(28)
7.1 Overview of Reconfigurable Systems
137(1)
7.2 FPGA Structure and Operation
138(4)
7.3 Xtreme DSP Development System
142(7)
7.4 TDTL FPGA Implementation
149(7)
7.4.1 The CORDIC Arctangent Block
151(1)
7.4.2 The Digital Controlled Oscillator
152(2)
7.4.3 The CORDIC Divider
154(2)
7.5 Real-Time TDTL Results
156(5)
7.5.1 First-Order TDTL
157(1)
7.5.2 Second-Order TDTL
157(2)
7.5.3 Sample Sensing Adaptive TDTL
159(2)
7.6 Conclusions
161(4)
8 Selected Applications 165(14)
8.1 PM Demodulation Using TDTL
165(4)
8.2 Performance in Gaussian Noise
169(2)
8.3 Simulation Results
171(1)
8.4 FSK and FM Demodulation
172(1)
8.5 Wideband FM Signal Detection
173(3)
8.6 Conclusions
176(3)
Bibliography 179(10)
Index 189

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