What is included with this book?
Foreword | p. xiii |
Preface | p. xv |
Acknowledgments | p. xvii |
Introduction | p. 1 |
Introduction and Motivation | p. 1 |
Book overview | p. 4 |
References | p. 5 |
Substrate Noise Propagation | p. 7 |
Introduction | p. 7 |
Modeling the Substrate | p. 8 |
Analytical Resistance Calculation Between Two Contacts | p. 9 |
Finite Difference Method | p. 13 |
Finite Element Method | p. 17 |
The Substrate Modeled with FDM | p. 19 |
Experimental Description | p. 19 |
Analysis of the Substrate Noise Propagation | p. 20 |
Conclusions | p. 27 |
The Substrate as a Finite Element Model | p. 28 |
Simulation Methodology | p. 28 |
Dealing with N-Doped Regions | p. 30 |
Simulation Setup for the Test Structure | p. 33 |
Comparison | p. 33 |
Conclusions | p. 33 |
Conclusions | p. 34 |
References | p. 36 |
Passive Isolation Structures | p. 39 |
Introduction | p. 39 |
Overview and Description of the Different Types of Passive Isolation Structures | p. 40 |
The Template Layout | p. 42 |
Integrating the Different Types of Guard Rings | p. 43 |
Simulation Setup | p. 44 |
Prediction and Understanding of Guard Rings | p. 44 |
Reference Structure | p. 45 |
P-Well Block Isolation | p. 47 |
N-Well Isolation | p. 50 |
P+ Guard Ring Shielding | p. 52 |
Triple Well Shielding | p. 56 |
Comparison and Conclusion | p. 60 |
Design of an Efficient P+ Guard Ring | p. 65 |
Impedance of the Ground Interconnect | p. 65 |
Width of the P+ Guard Ring | p. 67 |
Distance to the Victim | p. 70 |
Guidelines for Good P+ Guard Ring Design | p. 75 |
Conclusions | p. 76 |
References | p. 77 |
Noise Coupling in Active Devices | p. 79 |
Introduction | p. 79 |
Substrate Noise Impact on Analog Design | p. 80 |
Impact Simulation Methodology | p. 82 |
EM Simulation | p. 83 |
Circuit Simulation | p. 86 |
Transistor Test Bench | p. 86 |
Description of the Transistor Under Test | p. 87 |
Modeling the Transistor Test Bench | p. 87 |
Experimental Validation | p. 92 |
Substrate Noise Coupling Mechanisms in a Transistor | p. 92 |
Analyzing the Different Coupling Mechanisms in a Transistor | p. 94 |
Description and Measurement of the Device Under Test | p. 97 |
Modeling Different Substrate Noise Coupling Mechanisms | p. 100 |
Quantifying the Different Substrate Noise Coupling Mechanisms | p. 104 |
Experimental Validation of the Substrate Noise Coupling Mechanisms | p. 106 |
Conclusions | p. 108 |
References | p. 109 |
Measuring the Coupling Mechanisms in Analog/RF Circuits | p. 111 |
Introduction | p. 111 |
Measurement-Based Identification of the Dominant Substrate Noise Coupling Mechanisms | p. 114 |
Measurement of the Different Spurs | p. 115 |
Sensitivity Functions | p. 116 |
Determining the Influence of the PCB | p. 118 |
Example: 900 MHz LC-VCO | p. 119 |
Description of the LC-VCO | p. 119 |
Substrate Sensitivity Measurements | p. 120 |
Revealing the Dominant Coupling Mechanism for FM Spurs | p. 123 |
Revealing the Dominant Coupling Mechanism for AM Spurs | p. 128 |
Influence of the PCB Decoupling Capacitors on the Substrate Noise Impact | p. 130 |
Conclusions | p. 132 |
Study of the Coupling Mechanisms Between a Power Amplifier and an LC-VCO | p. 133 |
Description of the Design of the PPA and the LC-VCO | p. 135 |
Coupling Mechanisms Between the PPA and the LC-VCO | p. 137 |
Measuring the Dominant Coupling Mechanisms | p. 142 |
Conclusions | p. 146 |
Conclusions | p. 148 |
References | p. 148 |
The Prediction of the Impact of Substrate Noise on Analog/RF Circuits | p. 151 |
Introduction | p. 151 |
The Substrate Modeled with FDM | p. 152 |
Impact Simulation Methodology | p. 152 |
Prediction of the Impact of Substrate Noise from DC Up to LO Frequency | p. 156 |
Experimental Validation of the Simulation Methodology | p. 160 |
Conclusions | p. 162 |
Substrate Modeled by the FEM Method | p. 163 |
Impact Simulation Methodology | p. 163 |
Prediction of the Impact of Substrate Noise | p. 166 |
Verification with Measurements | p. 170 |
Conclusions | p. 172 |
Techniques to Reduce Substrate Noise Coupling | p. 173 |
Layout Techniques to Reduce the Substrate Noise Coupling | p. 174 |
Circuit Techniques to Reduce the Substrate Noise Coupling | p. 175 |
3D Stacking as a Solution to Substrate Noise Issues | p. 179 |
Separated Analog/Digital Ground | p. 185 |
Shared Analog/Digital Ground | p. 186 |
Experimental Validation | p. 186 |
Conclusions | p. 190 |
Conclusions | p. 191 |
References | p. 192 |
Noise Coupling in Analog/RF Systems | p. 195 |
Introduction | p. 195 |
Impact Simulation Methodology | p. 196 |
EM Simulation | p. 198 |
Parasitic Extraction | p. 200 |
Circuit Simulation | p. 200 |
Analyzing the Impact of Substrate Noise in Analog/RF Systems | p. 201 |
Analysis of the Propagation of Substrate Noise | p. 202 |
Analyzing the Substrate Noise Coupling | p. 202 |
Substrate Noise Impact on a 48-53 GHz LC-VCO | p. 203 |
Description of the LC-VCO | p. 203 |
Simulation Setup | p. 203 |
Conclusion | p. 207 |
Impact of Substrate Noise on a DC to 5 GHz Wideband Receiver | p. 208 |
Description of the Wideband Receiver | p. 208 |
Simulation Setup | p. 211 |
Parasitic Extraction | p. 214 |
Circuit Simulation | p. 214 |
Revealing the Dominant Coupling Mechanism | p. 215 |
Experimental Verification | p. 220 |
Conclusions and Discussion | p. 222 |
Conclusions | p. 222 |
Discussion | p. 223 |
References | p. 224 |
Narrowband Frequency Modulation of LC-Tank VCOs | p. 227 |
Port Conditions | p. 231 |
List of Acronyms | p. 233 |
About the Authors | p. 237 |
Index | p. 239 |
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