Advanced Digital Logic Design Using VHDL, State Machines, and Synthesis for FPGA's

by Lee, Sunggu

• ISBN13: 9780534466022
• ISBN10: 0534466028
• Edition: 1st
• Format: Hardcover
• Copyright: 2005-04-25
• Publisher: Cengage Learning

Summary

This textbook is intended to serve as a practical guide for the design of complex digital logic circuits such as digital control circuits, network interface circuits, pipelined arithmetic units, and RISC microprocessors. It is an advanced digital logic design textbook that emphasizes the use of synthesizable VHDL code and provides numerous fully worked-out practical design examples including a Universal Serial Bus interface, a pipelined multiply-accumulate unit, and a pipelined microprocessor for the ARM THUMB architecture.

Table of Contents

Condensed Overview of Introductory Digital Logic Design	1	(29)
Number Formats	3	(3)
Combinational Logic	6	(12)
Combinational Logic Devices	6	(5)
Combinational Logic Circuit Design	11	(7)
Sequential Logic	18	(9)
Sequential Logic Devices	19	(4)
Synchronous Sequential Circuit Design	23	(2)
Hazards and Glitches	25	(1)
Metastability	26	(1)
Resources	27	(1)
Bibliography	28	(1)
Problems	28	(2)
Digital Logic Design Using Hardware Description Languages	30	(15)
Hardware Description Languages	31	(1)
Design Flow	32	(1)
Synthesis	33	(2)
Register Transfer Level Notation	35	(1)
Logic Simulation	36	(3)
Properties of Actual Circuits	39	(2)
Chapter Review	41	(1)
Resources	42	(1)
Bibliography	42	(1)
Problems	43	(2)
Introduction to VHDL and Test Benches	45	(80)
VHDL Basics	47	(11)
Entity and Architecture	47	(1)
Signals, Data Types, Constants, and Operators	48	(4)
Libraries and Packages	52	(1)
Structural and Behavioral Descriptions	53	(5)
Testing and The Test Bench	58	(9)
Manufacturing Testing	59	(1)
Functional Testing	60	(1)
Test Benches	61	(2)
VHDL Test Bench	63	(4)
More Advanced VHDL Concepts	67	(15)
Concurrent and Sequential VHDL	67	(1)
Variables and Signals	68	(1)
Delay Modeling	69	(5)
Attributes	74	(1)
Procedures and Functions	75	(3)
Generics and Modeling a Bidirectional Bus	78	(4)
Construction of Complete VHDL Programs	82	(38)
Combinational Logic Circuits	83	(10)
Sequential Logic Circuits	93	(16)
Behavioral Modeling of More Complex Circuits	109	(11)
Chapter Review	120	(1)
Resources	121	(1)
Bibliography	121	(1)
Problems	122	(3)
High-Level VHDL Coding for Synthesis	125	(47)
Register-Transfer Level Notation	126	(1)
Combinational Logic Synthesis	127	(21)
Using Concurrent Signal Assignment Statements for Combinational Logic	127	(2)
Using Process Blocks for Combinational Logic	129	(4)
Complex Combinational Logic Code	133	(15)
Sequential Logic Synthesis	148	(5)
Using Process Blocks for Sequential Logic Synthesis	148	(5)
Synthesis Heuristics	153	(3)
Synthesis using A Commercial Tool	156	(7)
High-Level VHDL Coding	163	(5)
Chapter Review	168	(1)
Resources	169	(1)
Bibliography	169	(1)
Problems	169	(3)
State Machine Design	172	(50)
Manual State Machine Design	174	(17)
Pseudocode	176	(1)
RTL Program	176	(2)
Datapath	178	(1)
State Diagram	179	(2)
Control Logic	181	(5)
State Machine Design using ASM Charts	186	(5)
Automatic Synthesis-Based State Machine Design	191	(5)
Automatic Synthesis-Based Design Procedure	192	(1)
Algorithm to HDL Code Conversion	192	(4)
Design: Vending Machine	196	(13)
Automatic State Machine Design for a Vending Machine	197	(7)
Manual State Machine Design for a Vending Machine	204	(2)
Timing Diagram	206	(2)
Correspondence between Automatic and Manual Designs	208	(1)
Design: LCD Controller	209	(8)
Target LCD Module	209	(4)
VHDL Solution	213	(4)
Chapter Review	217	(1)
Resources	217	(1)
Bibliography	218	(1)
Problems	218	(4)
FPGA and Other Programmable Logic Devices	222	(30)
Programmable Logic Devices	223	(10)
Circuit Customization	223	(2)
Programmable Logic Arrays	225	(4)
Programmable Read-Only Memories	229	(1)
Programmable And-Array Logic	230	(3)
Field-Programmable Gate Arrays	233	(14)
Gate Arrays	233	(3)
FPGA Overview	236	(1)
Xilinx FPGA	236	(1)
FPGA Configuration	237	(3)
Xilinx Spartan-II FPGA Configuration Example	240	(5)
Boundary Scan	245	(2)
Chapter Review	247	(1)
Resources	248	(1)
Bibliography	248	(1)
Problems	249	(3)
Design of a USB Protocol Analyzer	252	(69)
Overview of USB Full-Speed Mode	254	(11)
Packet Transfer Protocol	255	(1)
Initialization Sequence	256	(1)
Physical Layer Interface	256	(3)
USB Packets	259	(1)
Cyclic Redundancy Checks	260	(2)
Observation of Actual USB Signals	262	(3)
Design Overview	265	(3)
State Machine	265	(1)
Subcircuit Partitioning	265	(3)
VHDL Solution	268	(46)
Digital Phase Locked Loop	271	(4)
NRZI-to-Binary Converter	275	(4)
CRC Checker Subcircuits	279	(7)
Packet ID Recognizer	286	(5)
State Machine Subcircuit	291	(10)
Top-Level Circuit	301	(3)
Test-Bench Code for Entire Circuit	304	(10)
Simulation Results	314	(2)
Chapter Review	316	(1)
Resources	317	(1)
Bibliography	317	(1)
Problems	318	(3)
Design of Fast Arithmetic Units	321	(40)
Adder Designs	322	(5)
Ripple Carry Adder	323	(1)
Carry-Lookahead Adder	324	(2)
Carry-Save Adder	326	(1)
Multiplier Designs	327	(7)
Combinational Multiplier	329	(1)
Sequential Multiplier	329	(1)
Fast Multiplication	329	(5)
Multiply-Accumulate Units	334	(1)
Pipelined Functional Units	334	(7)
Introduction to Pipelining	334	(3)
Pipelined Multiply-Accumulate Units	337	(4)
HDL Implementations	341	(15)
HDL Implementation Overview	341	(1)
HDL Design for a Pipelined Multiply-Accumulate Unit	342	(8)
Test Bench and Simulation Results	350	(6)
Chapter Review	356	(1)
Resources	357	(1)
Bibliography	357	(1)
Problems	357	(4)
Design of a Pipelined RISC Microprocessor	361	(50)
Introduction to Microprocessors	362	(4)
Reduced Instruction Set Computers	363	(1)
Basic Computer Operation	364	(2)
The THUMB Microprocessor Architecture	366	(3)
Thumb Programming Model	366	(1)
Overview of the Thumb Instruction Set	367	(2)
Instruction Pipeline Design	369	(6)
Pipeline Hazards	370	(1)
Hazard Prevention Techniques	371	(3)
Pipeline Hazard Solutions Adopted	374	(1)
HDL Implementation of the Thumb Pipeline	375	(31)
VHDL Thumb Implementation	376	(29)
Test Bench Verification	405	(1)
Chapter Review	406	(1)
Resources	407	(1)
Bibliography	408	(1)
Problems	408	(3)
A Thumb Instruction Set Listing	411	(21)
ADC <Rd>, <Rm>	411	(1)
ADD <Rd>, <Rn>, #immed3	411	(1)
ADD <Rd>, immed8	412	(1)
ADD <Rd>, <Rn>, <Rm>	412	(1)
ADD <Rd>, <Rm>	412	(1)
ADD <Rd>, PC, #immed8 x 4	412	(1)
ADD <Rd>, SP, #immed8 x 4	413	(1)
ADD SP, #immed7 x 4	413	(1)
AND <Rd>, <Rm>	413	(1)
ASR <Rd>, <Rm>, #immed5	413	(1)
ASR <Rd>, <Rs>	414	(1)
B<cond>, <target_address>	414	(1)
B <target_address>	415	(1)
BIC <Rd>, <Rm>	416	(1)
BKPT <immed8>	416	(1)
BL <target_address> or BLX <target_address>	416	(1)
BLX <Rm>	417	(1)
BX <Rm>	417	(1)
CMN <Rn>, <Rm>	418	(1)
CMP <Rn>, #immed8	418	(1)
CMP <Rn>, <Rm>	418	(1)
CMP <Rn>, <Rm>	419	(1)
EOR <Rd>, <Rm>	419	(1)
LDMIA <Rn>!, <registers>	419	(1)
LDR <Rd>, <Rn>, #immed5 x 4	420	(1)
LDR <Rd>, <Rn>, <Rm>	420	(1)
LDR <Rd>, PC, #immed8 x 4	420	(1)
LDRB <Rd>, SP, #immed8 x 4	421	(1)
LDRB <Rd>, <Rn>, #immed5	421	(1)
LDRB <Rd>, <Rn>, <Rm>	421	(1)
LDRH <Rd>, <Rn>, #immed5 x 2	421	(1)
LDRH <Rd>, <Rn>, <Rm>	422	(1)
LDRSB <Rd>, <Rn>, <Rm>	422	(1)
LDRSH <Rd>, <Rn>, <Rm>	422	(1)
LSL <Rd>, <Rm>, #immed5	423	(1)
LSL <Rd>, <Rs>	423	(1)
LSR <Rd>, <Rm>, #immed5	423	(1)
LSR <Rd>, <Rs>	424	(1)
MOV <Rd>, #immed8	424	(1)
MOV <Rd>, <Rn>	424	(1)
MOV <Rd>, <Rm>	424	(1)
MUL <Rd>, <Rm>	425	(1)
MVN <Rd>, <Rm>	425	(1)
NEG <Rd>, <Rm>	425	(1)
ORR <Rd>, <Rm>	425	(1)
POP <registers>	426	(1)
PUSH <registers>	426	(1)
ROR <Rd>, <Rs>	427	(1)
SBC <Rd>, <Rm>	427	(1)
STMIA <Rn>!, <registers>	427	(1)
STR <Rd>, <Rn>, #immed5 x 4	428	(1)
STR <Rd>, <Rn>, <Rm>	428	(1)
STR <Rd>, SP, #immed8 x 4	428	(1)
STRB <Rd>, <Rn>, #immed5	428	(1)
STRB <Rd>, <Rn>, <Rm>	429	(1)
STRH <Rd>, <Rn>, #immed5 x 2	429	(1)
STRH <Rd>, <Rn>, <Rm>	429	(1)
SUB <Rd>, <Rn>, #immed3	429	(1)
SUB <Rd>, #immed8	430	(1)
SUB <Rd>, <Rn>, <Rm>	430	(1)
SUB SP, #immed7 x 4	430	(1)
SWI <immed8>	430	(1)
TST <Rn>, <Rm>	431	(1)
B Answers to Selected Problems	432	(53)
Condensed Digital Logic Review	432	(3)
Digital Logic Design Using Hardware Description Languages	435	(2)
Introduction to VHDL and Test Benches	437	(13)
High-Level VHDL Coding for Synthesis	450	(10)
State Machine Design	460	(8)
FPGAs and Other Programmable Logic Devices	468	(3)
Design of a USB Protocol Analyzer	471	(2)
Design of Fast Arithmetic Units	473	(6)
Design of a Pipelined RISC CPU	479	(6)
Index	485