Advanced Metallization Conference 2001 (Amc 2001)

by McKerrow, Andrew; Shacham-Diamand, Yosi; Zaima, Shigeaki; Ohba, Takayuki

• ISBN13: 9781558996700
• ISBN10: 1558996702
• Format: Hardcover
• Copyright: 2002-03-01
• Publisher: Cambridge Univ Pr

Summary

Leading-edge advanced metallization schemes, as applied to VLSI interconnects, include the introduction of novel metals systems and novel dielectric materials. Technological advances highlighted at AMC 2001 include the latest developments in integrating copper metallization with low-dielectric constant materials, and evaluations of the reliability of such interconnects. Recently, in both industry and academia there has been increased interest in basic research as applied to the field of vertical integration. Since the problems that affect vertical integration are similar to those of VLSI interconnects, it is natural to include the topic here. In fact, it is anticipated that cross fertilization between the fields of VLSI metallization and vertical interconnect will yield a viable technical solution to the problem of multichip integration. This book offers a comprehensive look at the current state of the art of VLSI interconnects. Topics include: process integration; vertical integration and advanced packaging; copper metallization; low-K dielectrics technology; modeling; reliability; barriers; atomic-layer epitaxy and other technologies; and CMP and automation.

Table of Contents

Preface	p. xix
Acknowledgments	p. xxi
Materials Research Society Conference Proceedings	p. xxiii
Process Integration
Cu/SiLK Integration: Influence of Process on Reliability	p. 3
Extending Copper Metallization Technology for Wiring to End-of-Roadmap Feature Sizes	p. 11
Damascene Integration Feasibility of Developmental Porous SiLK Resin Films	p. 19
Integration of Organosilicate Glasses (OSGs) in High Performance Copper Interconnects	p. 25
0.13[mu]m Generation Integration of Dual Damascene Copper in SiLK and FSG	p. 33
A Cu Interconnect Process for the 130nm Process Technology Node	p. 39
Integration of Thin CVD TiSiN Barriers in Cu Interconnects	p. 43
Precleans for Copper Vias in an FSG Process	p. 49
A CMP-Free Cu/Low-k Integration Technology By Cu Pillar/Line and ps-Low-k STP Process	p. 57
Overcoming Barrier Integrity Issues of I-PVD Ta(N) Layers on Inorganic Porous Low-k's	p. 61
Electroless Cu Alloys for ULSI Applications	p. 67
Characterization and Integration of CVD Ultra Low-k Films (k<2.2) for Dual Damascene IMD Applications	p. 73
Evaluation and Evolution of ILD Materials	p. 79
Eliminating Process-Related Defects During the Fabrication of Copper Interconnects	p. 85
Integrative Aspects of Submicron Contact Filling by Al-Ge-Cu Sputtering	p. 91
Fringe Fields and Mechanical Support Structures: Obstacles on the Way to k=1	p. 97
Interconnect Length Distribution for Memory-Logic Mixed LSI	p. 103
Metal Gate Stack: Thermally Induced Reaction Study	p. 109
Titanium Nitride Metal Gate Electrode: Effect of Nitrogen Incorporation	p. 115
Estimation of Power Consumption Using Interconnect Length Distribution in System LSI	p. 121
Vertical Integration and Advanced Packaging
Bridging the Chip/Package Process Divide	p. 129
New Wafer Stacking Technology for Three-Dimensional System-on-a-Chip	p. 137
Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric Constant Materials	p. 143
Fabrication of Via-Chain Test Structures for 3D IC Technology Using Dielectric Glue Bonding on 200mm Wafers	p. 151
Interchip Via Technology by Using Copper for Vertical System Integration	p. 159
Copper Metallization
Novel Routes to "Zero-Length" Barriers for Cu/Low-k Integration	p. 169
Reactive Deposition of Device Quality Conformal Copper Films From Supercritical CO[subscript 2]	p. 177
Direct Electroless Copper Plating on Barrier Metals Without Pd Catalyst	p. 185
Preparation and Characterization of Electrochemically Deposited Copper Alloys	p. 191
Development of 3-Component Electroplating Chemistry and Processes to Meet Gap Filling and Bath Control Requirements for 0.1[mu]m Technology Node	p. 197
Comparison of Copper Via Chain and EM Resistance by DC and Pulse Plating	p. 203
Superfilling Characteristic and Evaluation of Chemically Enhanced CVD (CECVD) Cu Process	p. 209
Optimization of Plating Chemistry for Dual Damascene Cu Metallization	p. 215
Comparative Study on Cu(6N), CuAl[subscript 0.3wt.%] and CuCr[subscript 0.17wt.%] Films--Microstructure and Properties	p. 221
Metal Deposition From Organic Solutions for Microelectronic Applications	p. 227
On the Interaction of Silver Metallization With Silicon Dioxide	p. 233
Initial Growth of CVD-Cu Films for Thin Seed Layer	p. 239
Application of a High-Pressure Annealing Process for Damascene-Fabricated Cu Interconnections	p. 245
Low-k Dielectrics Technology
SiCOH Dielectrics: From Low-k to Ultralow-k by PECVD	p. 253
Fundamentals and Improvements of Diffusion Barrier/Copper Adhesion for Damascene Process	p. 261
Effective Porous Low-k in Single Damascene Integration	p. 267
Properties of Mesoporous Low-k MSSQ Based Film Prepared Using Macromolecular Porogen	p. 273
Evaluation of Ta(N) Diffusion Barrier Integrity on Porous Low-k Films	p. 279
Hydrophobisation Process for Porous Low-k Dielectric Silica Layers	p. 287
Integration of Cu With SiOCH (Coral) and SiC:H Low-k Dielectric Films in a Dual Damascene Scheme	p. 295
Cu Metallization Issues in Low-k SiOC Integration	p. 301
Barrier Process for Damascene Integration of Developmental Porous SiLK Resin Films	p. 307
Improved Mechanical Strength of Porous Diamond Film by Silane Coupler	p. 313
Processing-Mechanical Property Relationships in Ultra-Low-k Xerogel Films	p. 319
Oxidation and Plasma RF Bias Frequency Effects in the PECVD Growth of Si[subscript w]C[subscript x]O[subscript y]H[subscript z] Dielectric Films	p. 325
A New Measurement Technique of Pore Size Distribution of Porous Low-k Films	p. 331
Integration of Carbon Doped Oxide-CVD Low-k Dielectric Film for Damascene Cu Interconnection	p. 337
Mechanisms Producing Bowed Profiles in the Etching of Low-k Organic Films	p. 341
Modeling
High Performance SOI/Cu SRAMs and Memories in Microprocessors	p. 347
Simulations of Local Heating in VLSI Backend Structures Using ATAR	p. 355
Catalyst Induced Superconformal Filling: Electrodeposition and Chemical Vapor Deposition	p. 363
Calculating Current Flow in Deep-Submicron and Nanoscale Metal Structures	p. 371
Thermal and Electrical Simulation of Deep Submicron Interconnection Systems	p. 379
Mechanisms of Superconformal Copper Electrodeposition in Acidic Sulfate Baths Containing Accelerator and Suppressor Additives	p. 387
Towards Minimum k Values of Porous Dielectrics: A Simulation Study	p. 393
A Transport and Reaction Model for Atomic Layer Deposition	p. 399
A Multiscale Model for Chemical Mechanical Planarization	p. 405
Modeling and Simulation Opportunities for 3D Integrated Circuits	p. 411
Reliability
Optical Interconnects Review and Insertion Opportunities in Digital Systems	p. 419
Electromigration of Cu/Spin-on Porous Ultra Low-k Interconnects	p. 427
Electromigration and Stress Voiding Investigations on Dual Damascene Copper Interconnects	p. 433
Triangular Voltage Sweep Characterization of Copper Ion Migration Induced by Pre-Sputter Etch in Dual-Damascene Cu/FSG Interconnect Structures	p. 441
Reliability of Metal Insulator Metal Capacitors	p. 447
Stress Migration Study of Cu Interconnect With Various Low-k Dielectrics	p. 457
Investigation of the Copper Drift in the Low-k Polymers SiLK I, J and H	p. 465
High-k MIM Capacitors for Integration in Low Thermal Budget Applications	p. 471
Metal-Insulator-Metal (MIM) Capacitors for RF-BiCMOS Technology	p. 479
Electromigration Resistance Improvement of Dual-Damascene Copper Interconnection Using TaN/Ta Barrier Formed by Ionized Bias Sputtering	p. 487
One Force Driving Cu Diffusion Into Interlayer Dielectrics	p. 493
Microscopic Investigation of Electromigration Failure in Narrow Cu Interconnects	p. 497
Narrow Trench Corrosion	p. 503
Overcoming of Resist Poisoning Issue During Si-O-C Dielectric Integration in Cu Dual Damascene Interconnect for 0.1[mu]m Technology	p. 509
X-ray Diffraction Metrology for 200mm Process Qualification and Stability Assessment	p. 515
Analysis of Dielectric Breakdown of SiO[subscript 2] Film Induced by Copper Ion Drift	p. 521
Surface Morphology Control of Al-CVD for Dual-Damascene Application	p. 527
Electromigration of Cu Damascene Interconnects With (Ti)/CVD-TiN/(Ti) Underlayer	p. 533
Barriers
An Optimal Liner for Copper Damascene Interconnects	p. 541
Low Resistance Copper Interconnects with MOCVD TiN(Si) Barrier for Sub-0.13[mu]m Applications	p. 549
The Evaluation of the Diffusion Barrier Performance of MOCVD TiSiN Layers for Copper/Black Diamond Metallization	p. 555
Development of CVD TiN(Si) for Advance Cu Barrier Application	p. 559
Manufacturing-Ready Selectivity of CoWP Capping on Damascene Copper Interconnects	p. 567
XRR Metrology for Advanced Interconnect Material Process Characterization	p. 573
Evaluation of Novel Electrolessly Deposited Diffusion Barriers for Copper Interconnects	p. 581
Development of Tantalum Carbon Nitride (TaCN) Diffusion Barriers for Copper Metallization	p. 587
Physical and Electrical Characterization of ALD TiN Used as a Copper Diffusion Barrier in 0.25[mu]m, Dual Damascene Backend Structures	p. 593
Microstructure and Degradation Mechanisms of Ta Based Diffusion Barriers for Copper Interconnects	p. 597
Barrier Characteristics of PECVD [alpha]-SiC:H Dielectrics	p. 603
Process and Thin Film Characteristics of TaN Deposited by MOCVD	p. 609
Phase, Structure and Properties of Sputtered Ta and TaN[subscript x] Films	p. 613
Improvement of TaN[subscript x] Barrier Effectiveness Without Cu (111) Texture Degradation	p. 619
Atomic Layer Epitaxy and Other Technologies
Aspects of ALD Processes for Metallic Interconnects	p. 627
New Approaches to the Atomic Layer Deposition of Tantalum Nitride and Titanium Nitride Thin Films	p. 633
Development and Application of ALD TiN Process Using Batch Type ALD Equipment System for Mass Production	p. 641
Pulsed Nucleation for Ultra-High Aspect Ratio Tungsten Plugfill	p. 649
Atomic Layer Deposition of Tungsten Film from WF[subscript 6]/B[subscript 2]H[subscript 6]: Nucleation Layer for Advanced Semiconductor Devices	p. 655
The Application of SFD (Sequential Flow Deposition) of W to the Generation Below 0.13[mu]m	p. 661
HfO[subscript 2] and Hf[subscript 1-x]O[subscript 2] Deposition by MOCVD and TDEAH	p. 667
Theoretical Study on the Elementary Reaction Rates of Aluminum CVD	p. 673
Electrical Properties of Ni Silicide/Silicon Contact	p. 679
Miscellaneous--Cmp and Automation
Nanosize Diamond Particles for Copper CMP	p. 687
A Novel CMP Slurry With Inorganic/Resin Abrasive for Al Damascene Process	p. 693
Impact of Pad Conditioning on CMP Removal Rate and Planarity	p. 699
Wafer Ambient Control Box Optimum for Mini-Environment Tools	p. 705
Author Index	p. 711
Subject Index	p. 717
Table of Contents provided by Syndetics. All Rights Reserved.