Agp System Architecture

by MindShare, Inc.; Dzatko, Dave; Shanley, Tom

• ISBN13: 9780201700695
• ISBN10: 0201700697
• Edition: 2nd
• Format: Paperback
• Copyright: 1999-09-27
• Publisher: Addison-Wesley Professional

Summary

The Accelerated Graphics Port (AGP) interface is a platform bus specification that enables high-performance graphics capabilities, 3-D, and video--over networks as well as on individual PCs. Platform-independent, AGP is supported by numerous hardware and software vendors, and is now a standard on Intel-based platforms. Software and hardware engineers working with graphics must have a good understanding of this important technology.

Author Biography

Dave Dzatko has over ten years of experience designing and testing computer systems. He is currently an instructor with MindShare, Inc., teaching computer architecture to leading companies in the computer industry. Tom Shanley is one of the world's foremost authorities on PC system architecture and has personally trained thousands of engineers in hardware and software design.

Table of Contents

About This Book
The MindShare Architecture Series	1	(1)
Cautionary Note	2	(1)
Organization of This Book	2	(2)
Who This Book Is For	4	(1)
Prerequisite Knowledge	4	(1)
Documentation Conventions	4	(3)
Hexadecimal Notation	4	(1)
Binary Notation	5	(1)
Decimal Notation	5	(1)
Bits Versus Byte Notation	5	(1)
Bit Fields (Logical Groups of Bits or Signals)	5	(1)
Timing Diagram Drawing Convention	6	(1)
Clock-by-Clock Timing Diagram Description	6	(1)
Signal Polarity	7	(1)
Visit Our Web Site	7	(1)
We Want Your Feedback	7	(2)
The 3D Graphics Challenge
3D Graphics: Compute- and Memory-Intensive	9	(6)
Displaying 2D Objects	9	(1)
Perspective	9	(1)
Texture Map	10	(1)
In Summary	10	(1)
Displaying 3D Objects	10	(1)
General	10	(1)
Real-Time Motion	11	(1)
Geometry Pipeline Stages	11	(1)
Tessellation	11	(1)
Transformation	12	(1)
Lighting	12	(1)
Setup	12	(1)
Geometry Calculations Typically Performed by CPU	12	(1)
Rendering Pipeline Stages	12	(1)
Visibility	12	(1)
Texture Mapping	12	(1)
Shading	13	(1)
Smoothing	13	(1)
In Summary	13	(2)
PCI/AGP Adapter Overview
System Overview	15	(5)
NB Is Quad-Ported	15	(3)
DVD Interface	18	(1)
Display Connector	19	(1)
Video BIOS ROM	20	(1)
Local Versus Main Memory	20	(3)
Local Memory---Quick Access; Locally-Managed; Expensive	20	(2)
Main Memory---Slower Access; Managed By OS	22	(1)
PCI Graphics Adapter	23	(2)
Resides In Shared Bus Environment	23	(1)
Generates and Is Target of a Large Amount of PCI Bus Traffic	24	(1)
Most Main Memory Accesses Must Be Snooped	24	(1)
NB Knows AGP's Area of Memory Is Non-Cacheable	24	(1)
System Memory Used By PCI Masters May or May Not Be Cached	25	(1)
Snoops Slow Down PCI Accesses To Main Memory	25	(1)
Snoop Traffic On Processor Bus Can Hurt Processor(s)	25	(1)
Main Memory Less Available To Processors	25	(1)
Intro To AGP Graphics Adapter	25	(4)
Dedicated Bus = Improved Performance	25	(1)
High Speed Bus = Improved Performance	26	(1)
AGP Main Memory Accesses Aren't Snooped	26	(1)
AGP Can Ask Memory Arbiter To Expedite Accesses	26	(1)
AGP Request and Data Phases Are Decoupled	26	(1)
PCI Masters Startled By Increase In Performance!	27	(2)
AGP Enumeration and Configuration
Example Enumeration/Configuration of AGP	29	(1)
Host/PCI Bridge: PCI Bus 0, Device 0, Function 0	29	(3)
AGP Enable/Disable Bit	32	(1)
Discovering Host/PCI Bridge's AGP Register Set	33	(2)
NB Connects To AGP Bus via PCI-to-PCI Bridge	35	(1)
PCI-to-PCI Bridge's Configuration Registers	36	(4)
Status Register	37	(1)
Class Code Register	37	(1)
Header Type Register	37	(1)
Primary/Secondary/Subordinate Bus Registers	38	(1)
Secondary Status Register	38	(1)
VGA Enable Bit in Bridge Control Register	39	(1)
Assigning AGP Bus Number	40	(1)
Device At Other End of Bus Needn't Be a Graphics Adapter	40	(2)
Discovering AGP Graphics Adapter	42	(1)
Discovering Adapter's AGP Capability Register Set	42	(2)
Setting Up Adapter's BAR Registers	44	(1)
The Adapter's Command and Status Registers	45	(4)
AGP Memory Allocation and Usage
Introduction To Dynamic Memory Allocation	49	(3)
Local Versus System Memory	49	(1)
OS Manages System Memory	50	(1)
Memory Aperture Is Dynamically Sized	51	(1)
AGP Aperture Implementation	52	(9)
Purpose of the Aperture	52	(1)
Base Address Fixed, But Size Varies Based on Need	52	(1)
Aperture Is in Hyperspace!	52	(2)
Adapter's Assigned Main Memory Sliced and Diced	54	(1)
General	54	(1)
Processor's Paging Facility Solves Driver's Problem	54	(1)
AGP Adapter and NB Don't Have Access To Page Tables	54	(2)
Solution: Software Builds Lookup Table In Memory	56	(4)
Format of GART Table	60	(1)
Table Lookups Result in Lousy Performance	60	(1)
Solution: Put a Cache in NB	60	(1)
Window's Use of AGP
Intro To Windows Software Environment	61	(7)
Windows 95 + OSR 2.1 Required VGARTD. VXD	61	(1)
Windows 98 + DirectX 5.0 = No VGARTD. VXD	62	(1)
Overview of Software Hierarchy	62	(2)
How Graphics Adapter's HAL Is Created	64	(1)
In DirectDraw & Direct3D, Surface = Memory Buffer	64	(1)
Definition of Execute Buffer	64	(1)
Memory Types: Local, AGP (Aperture), System	64	(1)
Introduction	64	(1)
Local Memory	65	(1)
AGP Memory (aka Non-Local Display Memory)	65	(1)
System Memory	65	(1)
DirectDraw's Use of Memory	66	(1)
DMA, DIME and DIMEL	66	(1)
Introduction	66	(1)
DMA Model AGP	66	(1)
DIME (Direct Memory Execute) Model AGP	67	(1)
DIMEL (DIME and Local Memory) Model AGP	67	(1)
Aperture Designated as WC Memory Type	67	(1)
OpenGL	68	(1)
BIOS Initialization Requirements	68	(1)
Operating System Initialization Requirements	69	(3)
PCI Protocol Review
Some Basic Rules For Both Reads and Writes	72	(1)
Example Single Data Phase Read	72	(2)
Example Burst Read	74	(4)
Treatment of Byte Enables During Read or Write	78	(3)
Byte Enables Presented on Entry To Data Phase	78	(1)
Byte Enables May Change In Each Data Phase	79	(1)
Data Phase with No Byte Enables Asserted	79	(1)
Target with Limited Byte Enable Support	80	(1)
Rule for Sampling of Byte Enables	80	(1)
Cases Where Byte Enables Can Be Ignored	81	(1)
Performance During Read Transactions	81	(1)
Example Single Data Phase Write Transaction	82	(2)
Example Burst Write Transaction	84	(4)
Performance During Write Transactions	88	(2)
PCI Is Not An Efficient Bus	90	(4)
PCI Bus Arbitration	90	(1)
Shared Address/Data Bus	90	(1)
Data Phase Latency Rules	90	(1)
Disconnects	90	(1)
Retries	91	(3)
Intro to AGP Concepts & Terminology
Decoupling Address and Data Phases Optimizes Bus Usage	94	(2)
PCI Address and Data Phases Tightly-Coupled	94	(1)
AGP Address and Data Phases Decoupled	94	(1)
A Simple Comparison	95	(1)
Bus Arbitration	96	(3)
Arbitration To Issue Transaction Requests	96	(2)
Arbitration To Begin Previously-Requested Data Transfer	98	(1)
Issuing Transaction Requests	99	(5)
Issuing Requests via the AD and C/BE Buses	99	(2)
Issuing Requests via Sideband Address (SBA) Port	101	(1)
Introduction	101	(1)
Example Use of SBA Port in 1x Mode	102	(2)
AGP Data Transactions	104	(17)
In PCI, Transfer of Each Dword Can Be Delayed	104	(1)
In AGP, Data Is Transferred in Blocks	105	(1)
Wait State Before First Data Block	105	(1)
Inserting Wait States Between Blocks	106	(1)
On Read---Both Can Insert Wait States	106	(1)
On Write---Adapter Cannot Delay, North Bridge Can	106	(1)
Definition of Throttle Point	106	(1)
Data Transfer Size Can Be Less Than a Data Block	107	(1)
Usage of Byte Enables	107	(1)
Byte Enables In a Read Data Transaction	107	(1)
Byte Enables In a Write Data Transaction	107	(1)
Minimum Data Transaction Is One Clock Long	107	(1)
Intro To Data Transfers In 1x Mode	108	(1)
One Dword Transferred On Each Clock Rising-Edge	108	(1)
Data Block Size Is 16 Bytes	108	(1)
An Example Multiple Data Block 1x Transfer	108	(3)
Intro To Data Transfers In 2x Mode	111	(1)
Dwords Transferred Using Strobe Pair, Not Clock Rising-Edge	111	(2)
Data Block Size Is 32 Bytes	113	(1)
An Example Multiple Data Block 2x Transfer	113	(3)
Intro To Data Transfers In 4x Mode	116	(1)
Dwords Transferred Using Two Strobe Pairs	116	(1)
Using Strobes As Differential Signal Pairs	117	(1)
Data Block Size Is 32 Bytes	118	(1)
An Example Multiple Data Block 4x Transfer	118	(3)
PCI Bus Master Can Write to AGP Adapter's Local Memory	121	(1)
GART Support for PCI Masters Is Optional	121	(1)
Monochrome Device Adapter (MDA) Support	122	(1)
Some Terminology	122	(3)
AGP Master Versus AGP Target	122	(1)
Guaranteed Latency	123	(1)
Typical Latency	123	(1)
Mean Bandwidth	123	(2)
The Signal Groups
Required Versus Optional Features	125	(2)
Features the North Bridge Must Support	125	(1)
Features the North Bridge May Optionally Support	126	(1)
Features AGP Adapter Must Support	126	(1)
Features AGP Adapter May Optionally Support	126	(1)
PCI Target Latency Rules Don't Appley to North Bridge	127	(1)
AGP Graphics Adapter Cannot Use Subtractive Decode	127	(1)
North Bridge/AGP Adapter Interconnect Examples	127	(12)
Interconnect Example One	127	(2)
Interconnect Example Two	129	(2)
Interconnect Example Three	131	(2)
Interconnect Example Four	133	(2)
Interconnect Example Five	135	(2)
Interconnect Example Six	137	(2)
Introduction To Signal Description	139	(1)
AGP Clock Signal	139	(1)
Reset (RST#)	139	(1)
The Signaling Environment (I/O Voltage)	140	(1)
Where Is the AGP Bus Arbiter Located?	140	(1)
Signal Usage In AGP Transactions	141	(19)
Introduction To AGP Transaction Requests	141	(1)
Issuing Requests Via the AD and C/BE Buses	141	(1)
General	141	(1)
Requesting Bus Ownership	141	(3)
Issuing the Requests	144	(4)
Issuing Requests via the Sideband Address Port	148	(1)
No Bus Arbitration---You Own It All the Time	148	(4)
AD Bus Dedicated To Data Transfers	152	(1)
Issuing Requests via SBA Port	153	(1)
PCI Parity Not Used In AGP Transactions	153	(1)
AGP Data Transfers	153	(1)
General	153	(1)
Bus Arbitration For the Data Transfer	153	(1)
The Data Transfer	154	(2)
Detailed Description of AD_STB[1:0]	156	(2)
Detailed Description of AD_STB[1:0]#	158	(1)
Implementation of Strobes as Differential Signal Pairs	159	(1)
Signal Usage In PCI Transactions	160	(2)
PCI Bus Arbitration	160	(1)
North Bridge Arbitrates to Initiate PCI Transaction	160	(1)
AGP Graphics Adapter Arbitrates to Initiate PCI Transaction	161	(1)
PCI Address Phase and Data Phase(s)	161	(1)
PCI Parity	162	(1)
Signal Usage in Fast Write Transactions	162	(4)
Special Overflow Prevention Signals	166	(3)
WBF#---Prevents Initiation of Fast Write	166	(2)
RBF#---Read Buffer Full	168	(1)
Unimplemented PCI Signals	169	(1)
LOCK#	169	(1)
IDSEL --- Initialization Device Select	169	(1)
Interrupt Generation	169	(1)
Error Reporting	170	(2)
PCI PERR# Signal	170	(1)
PCI SERR# Signal	171	(1)
USB-Related Signals	172	(1)
USB+ and USB-, Universal Serial Bus Data Lines	172	(1)
OVRCNT# --- USB OverCurrent	172	(1)
Power Management	172	(1)
Signal Types	173	(2)
IN --- Input	173	(1)
OUT --- Output	173	(1)
T/S --- Tri-State	173	(1)
S/T/S --- Sustained Tri-State	173	(1)
O/D --- Open Drain Output	174	(1)
Pull-Up and Pull-Down Resistor Values	175	(2)
The Signaling Environment
Point-to-Point Topology	177	(1)
Number of Devices	178	(1)
Signal Routing and Layout	178	(1)
Trace Impedance and Line Termination	179	(1)
Add-in Card Clock Skew Specifications	179	(1)
AGP Voltage Characteristics	179	(1)
Vref Generation	180	(2)
For 3.3V AGP in 2x Data Transfer Mode	180	(1)
For 1.5V AGP in 2x and 4x Data Transfer Modes	181	(1)
Common Vref Recommended for 2x and 4x Mode Operation	181	(1)
Component Pinout Recommendations	182	(1)
Motherboard/Add-in Card Interoperability	182	(1)
Pull-up/Pull-down Resistors	183	(1)
Maximum AC Ratings and Device Protection	184	(1)
Power Supply	184	(1)
Mechanicals	184	(1)
Connector Pinout	185	(3)
DC Specifications	188	(1)
3.3 Volt Signaling	188	(1)
1.5 Volt Signaling	189	(1)
1x Transfer Mode Timing Parameters	189	(2)
Clock	189	(1)
Outputs	190	(1)
Inputs	190	(1)
Reset	190	(1)
2x and 4x Transfer Mode Timing Model	191	(14)
Min Shift From xRDY# Assertion to Arrival of Data Strobes at Receiver	191	(1)
Max Shift From xRDY# Assertion to Arrival of Data Strobes at Receiver	192	(2)
Outer Loop Controls Overall Data Transfer	194	(1)
In 2x and 4x Modes, Inner Loop Controls Transfer of Each Data Item	195	(1)
Strobe/Data Relationship in 2x Mode	196	(2)
Strobe/Data Relationship in 4x Mode	198	(2)
Using Strobes as Differential Signal Pairs in 4x Mode	200	(1)
Four Time Domains	201	(1)
Relationship of Outer Loop Signals at Transmitter and Receiver	202	(1)
Data/Strobe Timing Relationship at Transmitter and Receiver	202	(1)
Relationship of Outer Loop to Inner Loop Signals at Transmitter	203	(1)
Relationship of Inner Loop and Outer Loop Signals at Receiver	203	(1)
In 2x Mode	204	(1)
In 4x Mode	204	(1)
Driver Characteristics	205	(1)
Receiver Characteristics	206	(1)
Changes to Clock Frequencies in Mobile Designs	206	(1)
Intro To AGP Transfer Types
Command Types and the Transfer Length	207	(5)
Read Commands and Transfer Length	208	(1)
Low-Priority Reads	209	(1)
High-Priority Reads	209	(1)
Long Read Commands and Transfer Length	210	(1)
Write Commands	210	(1)
Low-Priority Writes	211	(1)
High-Priority Writes	211	(1)
Dual-Address Cycle	211	(1)
Flush and Fence Commands	212	(1)
Reserved Commands	212	(1)
AGP Ordering Rules	212	(4)
Relationship of AGP and CPU or PCI Transactions	212	(1)
Relationship of High-and Low-Priority AGP Transaction Streams	213	(1)
Relationship of Same Priority AGP Streams (Reads and Writes)	214	(1)
Ordering of Same Command Types	214	(1)
Ordering of Multiple Memory Read Requests	214	(1)
Ordering of Multiple Memory Write Requests	214	(1)
Ordering of High-Priority Reads and High-Priority Writes	214	(1)
Ordering of Low-Priority Reads and Low-Priority Writes	215	(1)
Fence Command	216	(1)
Flush Command	217	(2)
What's the Problem?	217	(1)
PCI-Based Graphics Adapter Solution	217	(1)
AGP-Based Graphics Adapter Solution	218	(1)
AGP Arbitration
The AGP Arbiter	219	(4)
Arbitration to Issue Transaction Request(s)	220	(2)
Arbitration To Start a Data Transfer	222	(1)
Maximizing Bus Usage via GNT# Pipelining	223	(4)
General	223	(1)
Removing GNT#	223	(1)
Limiting Number of Outstanding Grants	223	(1)
Idle Clock Necessary Sometimes	224	(1)
GNT# For Data Transaction During PCI or AGP Request Transaction	224	(1)
Early Removal of GNT# For Request Transaction	225	(1)
GNT# Pipelining During Read Data Transaction	225	(1)
GNT# and RBF#	225	(2)
AGP Request Transactions
Two Request Generation Mechanisms	227	(3)
AGP Request Queue Depth	230	(1)
Issuing Transaction Requests via AD and C/BE buses	231	(12)
Issuing Single Request over AD and C/BE Buses	231	(2)
Issuing Multiple Requests over AD and C/BE Buses	233	(3)
Back-to-Back Read Data Transactions	236	(4)
64-bit Memory Addressing Using AD Bus	240	(1)
Description	240	(1)
Example	241	(2)
Issuing Transaction Requests via the SBA Port	243	(14)
Introduction	243	(1)
Request Issued via Command Series	244	(1)
The NOP Command	244	(1)
Intro To 1x SBA Port Usage	245	(1)
Intro To 2x SBA Port Usage	245	(1)
Intro To 4x SBA Port Usage	245	(1)
Simultaneous Data Transfer and Request Issuance	246	(1)
SBA Command Format and Usage	246	(1)
Type 1 Supplies Address Bits A[14:3] + Transfer Length	246	(1)
Types 2, 3, 4 Supply Upper Part of Address + Request Type	246	(1)
Type 2 Command Supplies Transaction Type + A[23:15]	246	(1)
Type 3 Command Supplies A[35:24]	246	(1)
Type 4 Command --- A[47:36]	247	(1)
Type 1 Command Must Always Be Issued Last	247	(1)
Reserved Bits and Reserved Commands	247	(2)
Sideband Address Port Operation	249	(1)
Example Command Series For 256KB Read	250	(1)
SBA Port Transfer Modes	251	(1)
General	251	(1)
Side Band Addressing in 1x Mode	251	(2)
Side Band Addressing in 2x Mode	253	(1)
Side Band Addressing in 4x Mode	254	(1)
Nops In 4x Mode	254	(1)
4x Mode Example	254	(2)
SideBand Strobe Synchronization Protocol	256	(1)
Stopping the SBA Port Strobe(s)	256	(1)
Issue Sync Before Restarting Strobe(s)	256	(1)
AGP Data Flow Control
Introduction	257	(1)
In AGP, Data Is Transferred in Blocks	257	(1)
Wait State Before First Data Block	258	(1)
Inserting Wait States Between Blocks	258	(2)
On Read---Both Can Insert Wait States	258	(1)
On Write---Adapter Cannot Delay, North Bridge Can	259	(1)
Definition of Throttle Point	259	(1)
Data Transfer Size Can Be Less Than a Data Block	260	(1)
Usage of Byte Enables	261	(1)
Byte Enables In a Read Data Transaction	261	(1)
Byte Enables In a Write Data Transaction	261	(1)
But Minimum Data Transaction Is One Clock Long	261	(1)
Three Times Where Data Transfer Can Be Delayed	261	(1)
AGP Adapter's Control of Data Transfers	262	(3)
North Bridge's Control of Data Transfers	265	(1)
RBF# Prevents Return of Low-Priority Read Data	266	(3)
Buffer Size Required to Keep RBF# Off in 1x Mode	267	(1)
Buffer Size Required to Keep RBF# Off in 2x Mode	267	(1)
Buffer Size Required to Keep RBF# Off in 4x Mode	268	(1)
1x Data Transactions
Introduction	269	(1)
General	269	(1)
Multiple Data Block Read Transaction	270	(2)
Multiple Block Read Data Transfer with Wait States	272	(4)
Read Data Transaction, Wait State Before First Block	276	(3)
Write Data Transaction, No Initial Wait State	279	(2)
Back-to-Back Write Data Transactions, No Delays	281	(6)
2x Data Transactions
Introduction	287	(1)
2x Transfer Mode Data Transactions	287	(2)
Back-to-Back Read Transfers, No Wait States	289	(3)
Multiple Block Read, No Wait States	292	(3)
Multiple Block Write with Wait States	295	(3)
Back-to-Back Write Data Transactions, Minimum Delay	298	(5)
4x Data Transactions
Introduction	303	(1)
General	303	(1)
Using Strobe Falling-Edges To Latch Data	304	(1)
Using Strobe Crossover Point to Latch Data	304	(2)
Back-to-Back Read Data Transactions, No Wait States	306	(3)
Multiple Block Read, No Wait States	309	(3)
Multi-Block Read with Wait State Before 2nd Data Block	312	(2)
Back-to-Back Write Data Transactions, No Wait States	314	(5)
Fast Write Transactions
Use of WBF# to Prevent Start of Fast Write	319	(1)
Arbitration to Perform a Fast Write	319	(1)
Introduction to the Fast Write Transaction	320	(1)
Fast Write Transactions in 2x Mode	321	(7)
Fast Write in 2x Mode, No Wait States	321	(3)
Fast Write in 2x Mode, Wait States Added	324	(4)
Fast Write Transactions in 4x Mode	328	(2)
Adapter-Initiated Premature Transaction Termination	330	(10)
Retry	331	(1)
Disconnect	331	(1)
Disconnect After Subsequent Data Block Transferred (2x)	331	(3)
Disconnect Before Transferring Subsequent Data Block (2x)	334	(3)
Target Abort	337	(3)
Master-Initiated Premature Transaction Termination	340	(2)
Back-to-Back Fast Write Transactions	342	(4)
Two Fast Write Transactions with No Idle in Between	346	(3)
Use of the WBF# Signal	349	(3)
Short, Fast Write Transactions and DEVSEL#	352	(3)
Collision Avoidance
Many Transaction Pairs Require Turnaround Cycle(s)	355	(1)
AGP Write Data Followed by Fast Write	356	(2)
AGP Write Data Followed by AGP Read Data	358	(1)
AGP Pro
The Problem	359	(1)
AGP Pro Connector	359	(4)
General	359	(2)
AGP Versus AGP Pro Interoperability	361	(2)
Requires Two Adjacent PCI Connectors	363	(1)
Purpose of PCI Slots	363	(1)
PCI Slot Usage Rules	363	(1)
High-Power AGP Pro Card	364	(1)
Low-Power AGP Pro Card	364	(1)
Card Power Indication	365	(1)
Power Usage	365	(4)
Card That Only Connects to Pro Connector	366	(1)
Card That Connects To Pro and PCI Connectors	366	(3)
Index	369