Analog Behavioral Modeling With the Verilog-A Language

by Fitzpatrick, Dan; Miller, Ira

• ISBN13: 9780792380443
• ISBN10: 0792380444
• Edition: Disk
• Format: Hardcover
• Copyright: 1997-11-01
• Publisher: Kluwer Academic Pub

Summary

Analog Behavioral Modeling With The Verilog-A Language provides the IC designer with an introduction to the methodologies and uses of analog behavioral modeling with the Verilog-A language. In doing so, an overview of Verilog-A language constructs as well as applications using the language are presented. In addition, the book is accompanied by the Verilog-A Explorer IDE (Integrated Development Environment), a limited capability Verilog-A enhanced SPICE simulator for further learning and experimentation with the Verilog-A language. This book assumes a basic level of understanding of the usage of SPICE-based analog simulation and the Verilog HDL language, although any programming language background and a little determination should suffice. From the Foreword: 'Verilog-A is a new hardware design language (HDL) for analog circuit and systems design. Since the mid-eighties, Verilog HDL has been used extensively in the design and verification of digital systems. However, there have been no analogous high-level languages available for analog and mixed-signal circuits and systems. Verilog-A provides a new dimension of design and simulation capability for analog electronic systems. Previously, analog simulation has been based upon the SPICE circuit simulator or some derivative of it. Digital simulation is primarily performed with a hardware description language such as Verilog, which is popular since it is easy to learn and use. Making Verilog more worthwhile is the fact that several tools exist in the industry that complement and extend Verilog's capabilities ... Behavioral Modeling With the Verilog-A Language provides a good introduction and starting place for students and practicing engineers with interest in understanding this new level of simulation technology. This book contains numerous examples that enhance the text material and provide a helpful learning tool for the reader. The text and the simulation program included can be used for individual study or in a classroom environment ...' Dr. Thomas A. DeMassa, Professor of Engineering, Arizona State University

Table of Contents

1 Introduction	1	(10)
1.1 Motivation	1	(2)
1.2 Product Design Methodologies	3	(4)
1.3 The Role of Standards	7	(2)
1.3.1 Verilog-A as an Extension of Spice	8	(1)
1.4 The Role of Verilog-A	9	(2)
1.4.1 Looking Ahead to Verilog-AMS	10	(1)
2 Analog System Description and Simulation	11	(30)
2.1 Introduction	11	(1)
2.2 Representation of Systems	12	(7)
2.2.1 Anatomy of a Module	13	(1)
2.2.2 Structural Descriptions	14	(2)
2.2.3 Behavioral Descriptions	16	(3)
2.3 Mixed-Level Descriptions	19	(6)
2.3.1 Refining the Module	22	(3)
2.4 Types of Analog Systems	25	(4)
2.4.1 Conservative Systems	25	(1)
2.4.2 Branches	26	(1)
2.4.3 Conservation Laws In System Descriptions	27	(2)
2.4.4 Signal-Flow Systems	29	(1)
2.5 Signals in Analog Systems	29	(4)
2.5.1 Access Functions	31	(1)
2.5.2 Implicit Branches	32	(1)
2.5.3 Summary of Signal Access	33	(1)
2.6 Probes, Sources, and Signal Assignment	33	(5)
2.6.1 Probes	34	(1)
2.6.2 Sources	35	(2)
2.6.3 Illustrated Examples	37	(1)
2.7 Analog System Simulation	38	(3)
2.7.1 Convergence	40	(1)
3 Behavioral Descriptions	41	(46)
3.1 Introduction	41	(1)
3.2 Behavioral Descriptions	42	(3)
3.2.1 Analog Model Properties	43	(2)
3.3 Statements for Behavioral Descriptions	45	(8)
3.3.1 Analog Statement	45	(2)
3.3.2 Contribution Statements	47	(1)
3.3.3 Procedural or Variable Assignments	48	(1)
3.3.4 Conditional Statements and Expressions	49	(2)
3.3.5 Multi-way Branching	51	(2)
3.4 Analog Operators	53	(21)
3.4.1 Time Derivative Operator	53	(2)
3.4.2 Time Integral Operator	55	(2)
3.4.3 Delay Operator	57	(1)
3.4.4 Transition Operator	58	(4)
3.4.5 Slew Operator	62	(2)
3.4.6 Laplace Transform Operators	64	(4)
3.4.7 Z-Transform Operators	68	(6)
3.4.8 Considerations on the Usage of Analog Operators	74	(1)
3.5 Analog Events	74	(6)
3.5.1 Cross Event Analog Operator	75	(3)
3.5.2 Timer Event Analog Operator	78	(2)
3.6 Additional Constructs	80	(4)
3.6.1 Access to Simulation Environment	80	(1)
3.6.2 Indirect Contribution Statements	81	(2)
3.6.3 Case Statements	83	(1)
3.6.4 Iterative Statements	83	(1)
3.7 Developing Behavioral Models	84	(3)
3.7.1 Development Methodology	84	(1)
3.7.2 System and Use Considerations	85	(1)
3.7.3 Style	86	(1)
4 Declarations and Structural Descriptions	87	(20)
4.1 Introduction	87	(1)
4.2 Module Overview	87	(6)
4.2.1 Introduction to Interface Declarations	90	(1)
4.2.2 Introduction to Local Declarations	91	(1)
4.2.3 Introduction to Structural Instantiations	92	(1)
4.3 Module Interface Declarations	93	(5)
4.3.1 Port Signal Types and Directions	93	(3)
4.3.2 Parameter Declarations	96	(2)
4.4 Local Declarations	98	(1)
4.5 Module Instantiations	99	(8)
4.5.1 Positional and Named Association Example	100	(2)
4.5.2 Assignment of Parameters	102	(2)
4.5.3 Connection of Ports	104	(3)
5 Applications	107	(52)
5.1 Introduction	107	(1)
5.2 Behavioral Modeling of a Common Emitter Amplifier	108	(14)
5.2.1 Functional Model	112	(2)
5.2.2 Modeling Higher-Order Effects	114	(2)
5.2.3 Structural Model of Behavior	116	(2)
5.2.4 Behavioral Model	118	(4)
5.3 A Basic Operational Amplifier	122	(7)
5.3.1 Model Development	122	(5)
5.3.2 Settling Time Measurement	127	(2)
5.4 Voltage Regulator	129	(8)
5.4.1 Test Bench and Results	133	(4)
5.5 QPSK Modulator/Demodulator	137	(6)
5.5.1 Modulator	137	(3)
5.5.2 Demodulator	140	(3)
5.6 Fractional N-Loop Frequency Synthesizer	143	(10)
5.6.1 Digital VCO	145	(2)
5.6.2 Pulse Remover	147	(2)
5.6.3 Phase-Error Adjustment	149	(1)
5.6.4 Test Bench and Results	150	(3)
5.7 Antenna Position Control System	153	(6)
5.7.1 Potentiometer	154	(1)
5.7.2 DC Motor	154	(1)
5.7.3 Gearbox	155	(1)
5.7.4 Antenna	156	(1)
5.7.5 Test Bench and Results	157	(2)
Appendix A Lexical Conventions and Compiler Directives	159	(10)
A.1 Verilog-A Language Tokens	159	(6)
A.1.1 White Space	159	(1)
A.1.2 Comments	160	(1)
A.1.3 Operators	160	(1)
A.1.4 Numbers	161	(1)
A.1.5 Conversion	162	(1)
A.1.6 Identifiers, Keywords and System Names	162	(1)
A.1.7 Escaped Identifiers	162	(1)
A.1.8 Keywords	162	(1)
A.1.9 Verilog-A Keywords	163	(1)
A.1.10 Math Function Keywords	163	(1)
A.1.11 Analog Operator Keywords	164	(1)
A.1.12 System Tasks and Functions	165	(1)
A.2 Compiler Directives	165	(4)
A.2.1 `define and `undef	165	(1)
A.2.2 `ifdef, `else, `endif	166	(1)
A.2.3 `include	167	(1)
A.2.4 `resetall	168	(1)
Appendix B System Tasks and Functions	169	(6)
B.1 Introduction	169	(1)
B.2 Strobe Task	169	(1)
B.2.1 Examples	170	(1)
B.3 File Output	170	(1)
B.4 Simulation Time	171	(1)
B.5 Probabilistic Distribution	171	(1)
B.6 Random	172	(1)
B.7 Simulation Environment	173	(2)
Appendix C Laplace and Discrete Filters	175	(10)
C.1 Introduction	175	(1)
C.2 Laplace Filters	175	(3)
C.2.1 laplace_zp	175	(1)
C.2.2 laplace_zd	176	(1)
C.2.3 laplace_np	177	(1)
C.2.4 laplace_nd	177	(1)
C.3 Discrete Filters	178	(3)
C.3.1 zi_zp	178	(1)
C.3.2 zi_zd	179	(1)
C.3.3 zi_np	179	(1)
C.3.4 zi_nd	180	(1)
C.4 Verilog-A MATLAB Filter Specification Scripts	181	(4)
Appendix D Verilog-A Explorer IDE	185	(14)
D.1 Introduction	185	(2)
D.2 Installation and Setup	187	(4)
D.2.1 Overview of the Distribution	187	(1)
D.2.2 Executable and Include Path Setup	188	(1)
D.2.3 Overview of the IDE Organization	189	(2)
D.3 Using the Explorer IDE	191	(8)
D.3.1 Opening and Running an Existing Design	192	(6)
D.3.2 Creating a New Designs	198	(1)
Appendix E Spice Quick Reference	199
E.1 Introduction	199	(1)
E.2 Circuit Netlist Description	200	(1)
E.3 Components	201	(3)
E.3.1 Elements	201	(2)
E.3.2 Semiconductor Devices and Models	203	(1)
E.4 Analysis Types	204
E.4.1 Operating Point Analysis	204	(1)
E.4.2 DC Transfer Curve Analysis	204	(1)
E.4.3 Transient Analysis	204	(1)
E.4.4 AC Small-signal Analysis	205