Analog Layout Generation for Performance and Manufacturability

by Lampaert, Koen; Gielen, Georges; Sansen, Willy M. C.

• ISBN13: 9780792384793
• ISBN10: 0792384792
• Format: Hardcover
• Copyright: 1999-07-01
• Publisher: Kluwer Academic Pub

Summary

Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside world. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behaviour and the noise performance of analog circuits. Device mismatch and thermal effects put a fundamental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required. In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In Analog Layout Generation for Performance and Manufacturability, the authors propose a performance driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. This approach makes a complete and sensible trade-off between the different layout alternatives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction. Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. In Analog Layout Generation for Performance and Manufacturability, the authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout. They then integrate this technique with their performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications. Analog Layout Generation for Performance and Manufacturability will be of interest to analog engineers, researchers and students.

Table of Contents

Abstract	v
Introduction	1	(20)
Mixed-signal Design Methodology	1	(2)
A Hierarchical Performance-Driven Design Strategy	3	(4)
Physical Design Tools for Mixed-signal IC's	7	(2)
Circuit Level Layout Generation	7	(1)
System Level Layout Generation	7	(1)
Layout Extraction and Verification	8	(1)
Scope Of This Work	9	(1)
Layout Styles	9	(2)
Full-Custom	9	(1)
Semi-Custom	10	(1)
Scope Of This Work	11	(1)
Existing Tools for Analog Layout	11	(7)
The Analog Macro-Cell Layout Style	11	(2)
Implementations of the Macro-Cell Layout Style	13	(4)
Situation Of This Work	17	(1)
Overview of the Analog Layout Tool LAYLA	18	(2)
Circuit Analysis	19	(1)
Device Generation	19	(1)
Placement	19	(1)
Routing	19	(1)
Summary and Conclusions	20	(1)
Performance Driven Layout of Analog Integrated Circuits	21	(32)
Introduction	21	(1)
Problem formulation	21	(4)
Previous Work in Performance Driven Layout Generation	25	(3)
Digital Performance Driven Layout Generation	25	(1)
Analog Performance Driven Layout Generation	26	(1)
Discussion	27	(1)
A Direct Performance Driven Layout Strategy	28	(4)
Modeling Performance Degradation	29	(1)
Generation of Performance Sensitivities	29	(3)
Modeling of Layout Parasitics	32	(1)
Interconnect Parasitics	32	(6)
Interconnect Modeling	33	(1)
Equivalent Circuit Model	33	(3)
Parasitic Extraction	36	(2)
Device Parasitics	38	(1)
Mismatch	39	(4)
Mismatch Model	40	(1)
Layout Rules for Optimum Matching	41	(2)
Thermal Effects	43	(5)
Effect of Operating Temperature on Electrical Parameters	43	(3)
Thermal Analysis of Electronic Systems	46	(2)
Discussion	48	(1)
Substrate Coupling	48	(3)
Injection, Reception and Transmission of Substrate Current	48	(1)
Modeling of Substrate Coupling	49	(1)
Layout Measures to Reduce Substrate Coupling	50	(1)
Summary and Conclusions	51	(2)
Module Generation	53	(18)
Introduction	53	(1)
Problem Formulation	53	(2)
Module Generation Strategies	55	(2)
Fixed Library of Procedural Generators	55	(1)
Dynamic Merging	56	(1)
Simultaneous Placement and Module Optimization	56	(1)
Discussion	57	(1)
Transistor Stacking Algorithms	57	(3)
Procedural Module Generation	60	(1)
Technology Independence	60	(1)
Example	61	(7)
MOS Transistor	62	(6)
Cascode MOS Transistor Pair	68	(1)
Summary and Conclusions	68	(3)
Placement	71	(48)
Introduction	71	(1)
Problem Formulation	71	(3)
Overview of the Placement Tool	74	(1)
Previous Work in Placement Algorithms	75	(5)
Constructive Placement (CP)	76	(1)
Force-Directed Placement (FDP)	76	(1)
Placement by Partitioning (PbP)	76	(1)
Quadratic Optimization (QO)	76	(1)
Simulated Evolution (SE)	77	(1)
Simulated Annealing (SA)	77	(1)
Discussion	78	(2)
Simulated Annealing for Analog Performance Driven Placement	80	(7)
Placement Representation	80	(3)
Device Representation	83	(2)
Interconnect Area Estimation	85	(2)
Handling Analog Constraints in Simulated Annealing	87	(2)
Move Set	89	(5)
Cost Function	94	(1)
Estimating Performance Degradation	95	(9)
Interconnect Parasitics	96	(4)
Device Mismatch	100	(1)
Thermal Effects	101	(3)
Dynamic Interconnect Area Estimation	104	(1)
Annealing Schedule	105	(2)
Experimental Results	107	(11)
Comparator	107	(4)
Opamp1	111	(2)
Opamp2	113	(2)
Opamp3	115	(3)
Summary and Conclusions	118	(1)
Routing	119	(34)
Introduction	119	(1)
Problem Formulation	119	(1)
Overview of the Routing Tool	120	(1)
Classification of Routing Algorithms	121	(3)
Routing Strategy	121	(1)
Routing Model	122	(1)
Search Strategies	123	(1)
Previous Work in Area Routing	124	(2)
Maze Routing	124	(1)
Line-Search Routing	125	(1)
Line-Expansion Routing	125	(1)
Discussion	126	(1)
A Grid-Less Maze Routing Algorithm	126	(8)
Routing Model	127	(3)
Source Region Expansion	130	(1)
Path Expansion	131	(3)
Cost Function	134	(4)
Actual Path Cost	134	(2)
Predictor Term	136	(1)
Symmetric Routing	136	(1)
Multi-Terminal Nets	137	(1)
Net Scheduling	138	(2)
Pre-Routing Phase	139	(1)
Performance Driven Routing Phase	139	(1)
Manufacturability Phase	140	(1)
Estimating Yield and Testability	140	(7)
Yield Modeling	141	(4)
Testability	145	(2)
Experimental Results	147	(5)
Opamp1	147	(3)
Opamp2	150	(2)
CPU Times	152	(1)
Summary and Conclusions	152	(1)
Implementation	153	(6)
Introduction	153	(1)
Implementation	153	(2)
Source Code	153	(1)
Interface to Electronic Design Frameworks	154	(1)
Use of LAYLA in an Industrial Environment	155	(1)
Link to Schematic Capture	155	(1)
Link to Simulation	155	(1)
Back-Annotation of Layout Parasitics	156	(1)
Results	156	(3)
General Conclusions	159	(4)
Bibliography	163