Analysis and Design of Resilient VLSI Circuits

by Garg, Rajesh; Khatri, Sunil P.

• ISBN13: 9781441909305
• ISBN10: 1441909303
• eBook ISBN(s): 9781441909312
• Format: Hardcover
• Copyright: 2009-12-03
• Publisher: Springer Verlag
• More Book Details
• Purchase Benefits

Summary

This book is motivated by the changes face in designing reliable integrated systems using modern VLSI processes. The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. This, VISI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation induced soft errors.

Table of Contents

Introduction	p. 1
Background and Motivation	p. 2
Radiation Particle Strikes	p. 2
Process Variations	p. 10
Monograph Overview	p. 12
Chapter Summary	p. 15
References	p. 15
Soft Errors
Analytical Determination of Radiation-induced Pulse With in Combinational Circuits	p. 21
Introduction	p. 21
Related Previous Work	p. 23
Proposed Analytical Model for the Pulse Width of Radiation-induced Voltage Glitch	p. 24
Radiation Particle strike at the Output of an Inverter	p. 25
Classification of Radiation Particle Strikes	p. 26
Overview of the Model for Determining the Pulse Width of the Voltage Glitch	p. 27
Determining of the Proposed Model for Determining the Pulse Width of the Voltage Glitch	p. 29
Experimental Results	p. 35
Chapter Summary	p. 39
References	p. 39
Analytical Determination of the Radiation-induced Pulse Shape	p. 41
Introduction	p. 41
Related Previous Work	p. 42
Proposed Analytical Model for the Shape of Radiation-induced Voltage Glitch	p. 43
Overview of the Proposed Model for Determining the Pulse Shape of the Voltage Glitch	p. 44
Derivation of the Model for Determining the Shape of the Radiation-induced Voltage Glitch	p. 46
Experimental Results	p. 53
Chapter Summary	p. 57
References	p. 57
Modeling Dynamic stability of SRAMs in the Presence of Radiation Particle Strikes	p. 59
Introduction	p. 59
Related Previous Work	p. 60
Proposed Model for the Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes	p. 61
Weak Coupling Mode Analysis	p. 63
Strong Feedback Mode Analysis	p. 66
Experimental Results	p. 67
Chapter Summary	p. 69
References	p. 69
3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits	p. 71
Introduction	p. 71
Related Previous Work	p. 72
simulation Setup	p. 73
NMOS Device Modeling and Characterization	p. 75
Experimental Results	p. 76
Chapter Summary	p. 84
References	p. 85
Clamping Diode-based Radiation Tolerant Circuit Design Approach	p. 87
Introduction	p. 87
Related Previous Work	p. 88
Proposed Clamping Diode-based Radiation Hardening	p. 89
Operation of Radiation-induced Voltage Clamping Devices	p. 89
Critical Depth for Gate	p. 92
Circuit Level Radiation Hardening	p. 92
Alternative Circuit Level Radiation Hardening	p. 94
Final Circuit Selection	p. 96
Experimental Results	p. 96
Chapter Summary	p. 105
References	p. 107
Split-output-based Radiation Tolerant Circuit Design Approach	p. 109
Introduction	p. 109
Related Previous Work	p. 110
Proposed Split-output-based Radiation Hardening	p. 110
Radiation Tolerant Standard Cell Design	p. 110
Circuit Level Radiation Hardening	p. 115
Critical Charge for Radiation Hardened Circuits	p. 119
Experimental Results	p. 122
Chapter Summary	p. 126
References	p. 127
Process Variations
Sensitizable Statistical Timing Analysis	p. 131
Introduction	p. 131
Related Previous Work	p. 132
Proposed Sensitizable Timing Analysis Approach	p. 134
Phase 1: Finding Sensitizable Delay-critical Vector Transitions	p. 134
Propagating Arrival Times	p. 135
Phase: Computing the Output Delay Distribution	p. 141
Experimental Results	p. 141
Determining the Number of Input Vector Transitions N	p. 148
Chapter Summary	p. 150
References	p. 150
A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates	p. 153
Introduction	p. 153
Related Previous Work	p. 154
Process Variation Tolerant Combinational Circuit Design	p. 155
Process Variations	p. 155
Variation Tolerant Standard Cell Design	p. 156
Variation Tolerant Combinational Circuits	p. 159
Experimental Results	p. 160
Chapter Summary	p. 169
References	p. 169
Process Variation Tolerant Single-supply True Voltage Level Shifter	p. 173
Introduction	p. 173
The Need for a Single-supply Voltage Level Shifter	p. 174
Related Previous Work	p. 176
Proposed Single-supply True Voltage Level Shifter	p. 177
Experimental Results	p. 180
Performance Comparison with Nominal Parameters Value	p. 181
Performance Comparison Under Process and Temperature Variations	p. 182
Voltage Translation Range for SS-TVLS	p. 183
Layout of SS-TVLS	p. 184
Chapter Summary	p. 186
References	p. 188
Conclusions and Future Directions	p. 189
References	p. 193
Sentaurus Related Code	p. 195
Code for 3D NMOS Device Creation Using Sentaurus-Structure Editor Tool	p. 195
Code for Mixed-Level Simulation of a Radiation Particle Strike Using Sentaurus-Device	p. 203
Index	p. 207
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