Application-Specific Integrated Circuits

by Smith, Michael John Sebastian

• ISBN13: 9780201500226
• ISBN10: 0201500221
• Format: Hardcover
• Copyright: 1997-01-01
• Publisher: Addison-Wesley Professional

Summary

This book is the first comprehensive introduction to application - specific integrated circuits (ASICs) and the latest methods in the design of VLSI systems. Exploiting commercially - available tools, ASIC methods both speed the development of new chips and lower development costs. Engineers contemplating the use of ASICs in a design project or simply interested in knowing more about the different ASIC types and design styles will find this book to be a useful introduction. Anyone already working with ASICs will also find it a valuable information source. For example, the chapters and syntax appendices on Verilog and VHDL can be used as a quick reference for engineering work on high - level ASIC design entry.

Table of Contents

1 INTRODUCTION TO ASICs	1	(38)
1.1 Types of ASICs	4	(12)
1.1.1 Full-Custom ASICs	5	(1)
1.1.2 Standard-Cell-Based ASICs	6	(5)
1.1.3 Gate-Array-Based ASICs	11	(1)
1.1.4 Channeled Gate Array	12	(1)
1.1.5 Channelless Gate Array	12	(1)
1.1.6 Structured Gate Array	13	(1)
1.1.7 Programmable Logic Devices	14	(2)
1.1.8 Field-Programmable Gate Arrays	16	(1)
1.2 Design Flow	16	(2)
1.3 Case Study	18	(2)
1.4 Economics of ASICs	20	(7)
1.4.1 Comparison Between ASIC Technologies	20	(1)
1.4.2 Product Cost	20	(1)
1.4.3 ASIC Fixed Costs	21	(4)
1.4.4 ASIC Variable Costs	25	(2)
1.5 ASIC Cell Libraries	27	(3)
1.6 Summary	30	(1)
1.7 Problems	31	(5)
1.8 Bibliography	36	(2)
1.9 References	38	(1)
2 CMOS LOGIC	39	(78)
2.1 CMOS Transistors	41	(8)
2.1.1 P-Channel Transistors	45	(1)
2.1.2 Velocity Saturation	45	(2)
2.1.3 SPICE Models	47	(1)
2.1.4 Logic Levels	47	(2)
2.2 The CMOS Process	49	(9)
2.2.1 Sheet Resistance	55	(3)
2.3 CMOS Design Rules	58	(2)
2.4 Combinational Logic Cells	60	(10)
2.4.1 Pushing Bubbles	63	(2)
2.4.2 Drive Strength	65	(1)
2.4.3 Transmission Gates	66	(3)
2.4.4 Exclusive-OR Cell	69	(1)
2.5 Sequential Logic Cells	70	(5)
2.5.1 Latch	70	(1)
2.5.2 Flip-Flop	71	(2)
2.5.3 Clocked Inverter	73	(2)
2.6 Datapath Logic Cells	75	(24)
2.6.1 Datapath Elements	77	(2)
2.6.2 Adders	79	(6)
2.6.3 A Simple Example	85	(2)
2.6.4 Multipliers	87	(7)
2.6.5 Other Arithmetic Systems	94	(1)
2.6.6 Other Datapath Operators	95	(4)
2.7 I/O Cells	99	(3)
2.8 Cell Compilers	102	(1)
2.9 Summary	102	(1)
2.10 Problems	103	(10)
2.11 Bibliography	113	(1)
2.12 References	114	(3)
3 ASIC LIBRARY DESIGN	117	(52)
3.1 Transistors as Resistors	117	(5)
3.2 Transistor Parasitic Capacitance	122	(7)
3.2.1 Junction Capacitance	124	(1)
3.2.2 Overlap Capacitance	124	(1)
3.2.3 Gate Capacitance	124	(2)
3.2.4 Input Slew Rate	126	(3)
3.3 Logical Effort	129	(12)
3.3.1 Predicting Delay	134	(1)
3.3.2 Logical Area and Logical Efficiency	134	(1)
3.3.3 Logical Paths	135	(2)
3.3.4 Multistage Cells	137	(1)
3.3.5 Optimum Delay	138	(2)
3.3.6 Optimum Number of Stages	140	(1)
3.4 Library-Cell Design	141	(1)
3.5 Library Architecture	142	(2)
3.6 Gate-Array Design	144	(6)
3.7 Standard-Cell Design	150	(2)
3.8 Datapath-Cell Design	152	(3)
3.9 Summary	155	(1)
3.10 Problems	155	(12)
3.11 Bibliography	167	(1)
3.12 References	168	(1)
4 PROGRAMMABLE ASICs	169	(22)
4.1 The Antifuse	170	(4)
4.1.1 Metal-Metal Antifuse	172	(2)
4.2 Static RAM	174	(1)
4.3 EPROM and EEPROM Technology	174	(2)
4.4 Practical Issues	176	(2)
4.4.1 FPGAs in Use	177	(1)
4.5 Specifications	178	(1)
4.6 PREP Benchmarks	179	(1)
4.7 FPGA Economics	180	(4)
4.7.1 FPGA Pricing	180	(3)
4.7.2 Pricing Examples	183	(1)
4.8 Summary	184	(1)
4.9 Problems	185	(5)
4.10 Bibliography	190	(1)
4.11 References	190	(1)
5 PROGRAMMABLE ASIC LOGIC CELLS	191	(40)
5.1 Actel ACT	191	(13)
5.1.1 ACT 1 Logic Module	191	(1)
5.1.2 Shannon's Expansion Theorem	192	(1)
5.1.3 Multiplexer Logic as Function Generators	193	(3)
5.1.4 ACT 2 and ACT 3 Logic Modules	196	(1)
5.1.5 Timing Model and Critical Path	197	(4)
5.1.6 Speed Grading	201	(1)
5.1.7 Worst-Case Timing	201	(3)
5.1.8 Actel Logic Module Analysis	204	(1)
5.2 Xilinx LCA	204	(5)
5.2.1 XC3000 CLB	204	(2)
5.2.2 XC4000 Logic Block	206	(1)
5.2.3 XC5200 Logic Block	207	(1)
5.2.4 Xilinx CLB Analysis	207	(2)
5.3 Altera FLEX	209	(1)
5.4 Altera MAX	209	(9)
5.4.1 Logic Expanders	211	(4)
5.4.2 Timing Model	215	(2)
5.4.3 Power Dissipation in Complex PLDs	217	(1)
5.5 Summary	218	(6)
5.6 Problems	224	(5)
5.7 Bibliography	229	(1)
5.8 References	230	(1)
6 PROGRAMMABLE ASIC I/O CELLS	231	(44)
6.1 DC Output	232	(3)
6.1.1 Totem-Pole Output	234	(1)
6.1.2 Clamp Diodes	235	(1)
6.2 AC Output	235	(8)
6.2.1 Supply Bounce	239	(1)
6.2.2 Transmission Lines	240	(3)
6.3 DC Input	243	(5)
6.3.1 Noise Margins	244	(2)
6.3.2 Mixed-Voltage Systems	246	(2)
6.4 AC Input	248	(5)
6.4.1 Metastability	249	(4)
6.5 Clock Input	253	(2)
6.5.1 Registered Inputs	253	(2)
6.6 Power Input	255	(3)
6.6.1 Power Dissipation	256	(2)
6.6.2 Power-On Reset	258	(1)
6.7 Xilinx I/O Block	258	(3)
6.7.1 Boundary Scan	260	(1)
6.8 Other I/O Cells	261	(1)
6.9 Summary	262	(1)
6.10 Problems	263	(9)
6.11 Bibliography	272	(1)
6.12 References	273	(2)
7 PROGRAMMABLE ASIC INTERCONNECT	275	(24)
7.1 Actel ACT	275	(9)
7.1.1 Routing Resources	276	(2)
7.1.2 Elmore's Constant	278	(2)
7.1.3 RC Delay in Antifuse Connections	280	(1)
7.1.4 Antifuse Parasitic Capacitance	281	(2)
7.1.5 ACT 2 and ACT 3 Interconnect	283	(1)
7.2 Xilinx LCA	284	(4)
7.3 Xilinx EPLD	288	(1)
7.4 Altera MAX 5000 and 7000	289	(1)
7.5 Altera MAX 9000	290	(1)
7.6 Altera FLEX	291	(1)
7.7 Summary	292	(2)
7.8 Problems	294	(3)
7.9 Bibliography	297	(1)
7.10 References	297	(2)
8 PROGRAMMABLE ASIC DESIGN SOFTWARE	299	(28)
8.1 Design Systems	299	(5)
8.1.1 Xilinx	301	(2)
8.1.2 Actel	303	(1)
8.1.3 Altera	303	(1)
8.2 Logic Synthesis	304	(3)
8.2.1 FPGA Synthesis	305	(2)
8.3 The Halfgate ASIC	307	(9)
8.3.1 Xilinx	307	(3)
8.3.2 Actel	310	(1)
8.3.3 Altera	310	(5)
8.3.4 Comparison	315	(1)
8.4 Summary	316	(1)
8.5 Problems	316	(4)
8.6 Bibliography	320	(6)
8.6.1 FPGa Vendors	321	(2)
8.6.2 Third-Party Software	323	(3)
8.7 References	326	(1)
9 LOW-LEVEL DESIGN ENTRY	327	(52)
9.1 Schematic Entry	328	(17)
9.1.1 Hierarchical Design	330	(1)
9.1.2 The Cell Library	330	(2)
9.1.3 Names	332	(1)
9.1.4 Schematic Icons and Symbols	333	(3)
9.1.5 Nets	336	(1)
9.1.6 Schematic Entry for ASICs and PCBs	336	(2)
9.1.7 Connections	338	(1)
9.1.8 Vectored Instances and Buses	338	(2)
9.1.9 Edit-in-Place	340	(1)
9.1.10 Attributes	341	(1)
9.1.11 Netlist Screener	341	(2)
9.1.12 Schematic-Entry tools	343	(2)
9.1.13 Back-Annotation	345	(1)
9.2 Low-Level Design Languages	345	(8)
9.2.1 ABEL	346	(2)
9.2.2 CUPL	348	(2)
9.2.3 PALASM	350	(3)
9.3 PLA Tools	353	(2)
9.4 EDIF	355	(14)
9.4.1 EDIF Syntax	355	(2)
9.4.2 An EDIF Netlist Example	357	(2)
9.4.3 An EDIF Schematic Icon	359	(6)
9.4.4 An EDIF Example	365	(4)
9.5 CFI Design Representation	369	(4)
9.5.1 CFI Connectivity Model	370	(3)
9.6 Summary	373	(1)
9.7 Problems	373	(3)
9.8 Bibliography	376	(1)
9.9 References	377	(2)
10 VHDL	379	(100)
10.1 A Counter	380	(1)
10.2 A 4-bit Multiplier	381	(9)
10.2.1 An 8-bit Adder	381	(1)
10.2.2 A Register Accumulator	381	(2)
10.2.3 Zero Detector	383	(1)
10.2.4 A Shift Register	384	(1)
10.2.5 A State Machine	384	(1)
10.2.6 A Multiplier	385	(3)
10.2.7 Packages and Testbench	388	(2)
10.3 Syntax and Semantics of VHDL	390	(2)
10.4 Identifiers and Literals	392	(1)
10.5 Entities and Architectures	393	(5)
10.6 Packages and Libraries	398	(7)
10.6.1 Standard Package	399	(1)
10.6.2 Std_logic_1164 Package	400	(2)
10.6.3 Textio Package	402	(1)
10.6.4 Other Packages	403	(1)
10.6.5 Creating Packages	404	(1)
10.7 Interface Declarations	405	(6)
10.7.1 Port Declaration	406	(4)
10.7.2 Generics	410	(1)
10.8 Type Declarations	411	(2)
10.9 Other Declarations	413	(6)
10.9.1 Object Declarations	414	(1)
10.9.2 Subprogram Declarations	415	(3)
10.9.3 Alias and Attribute Declarations	418	(1)
10.9.4 Predefined Attributes	419	(1)
10.10 Sequential Statements	419	(11)
10.10.1 Wait Statement	421	(2)
10.10.2 Assertion and Report Statements	423	(1)
10.10.3 Assignment Statements	424	(2)
10.10.4 Procedure Call	426	(1)
10.10.5 If Statement	427	(1)
10.10.6 Case Statement	428	(1)
10.10.7 Other Sequential Control Statements	429	(1)
10.11 Operators	430	(2)
10.12 Arithmetic	432	(5)
10.12.1 IEEE Synthesis Packages	434	(3)
10.13 Concurrent Statements	437	(8)
10.13.1 Block Statement	438	(2)
10.13.2 Process Statement	440	(1)
10.13.3 Concurrent Procedure Call	441	(1)
10.13.4 Concurrent Signal Assignment	442	(1)
10.13.5 Concurrent Assertion Statement	443	(1)
10.13.6 Component Instantiation	444	(1)
10.13.7 Generate Statement	444	(1)
10.14 Execution	445	(2)
10.15 Configurations and Specifications	447	(2)
10.16 An Engine Controller	449	(7)
10.17 Summary	456	(3)
10.18 Problems	459	(18)
10.19 Bibliography	477	(1)
10.20 References	478	(1)
11 VERILOG HDL	479	(80)
11.1 A Counter	480	(2)
11.2 Basics of the Verilog Language	482	(8)
11.2.1 Verilog Logic Values	483	(1)
11.2.2 Verilog Data Types	483	(3)
11.2.3 Other Wire Types	486	(1)
11.2.4 Numbers	486	(2)
11.2.5 Negative Numbers	488	(1)
11.2.6 Strings	489	(1)
11.3 Operators	490	(4)
11.3.1 Arithmetic	492	(2)
11.4 Hierarchy	494	(1)
11.5 Procedures and Assignments	495	(3)
11.5.1 Continuous Assignment Statement	496	(1)
11.5.2 Sequential Block	497	(1)
11.5.3 Procedural Assignments	498	(1)
11.6 Timing Controls and Delay	498	(8)
11.6.1 Timing Control	498	(3)
11.6.2 Data Slip	501	(1)
11.6.3 Wait Statement	502	(1)
11.6.4 Blocking and Nonblocking Assignments	503	(1)
11.6.5 Procedural Continuous Assignment	504	(2)
11.7 Tasks and Functions	506	(1)
11.8 Control Statements	506	(3)
11.8.1 Case and If Statement	506	(1)
11.8.2 Loop Statement	507	(1)
11.8.3 Disable	508	(1)
11.8.4 Fork and Join	509	(1)
11.9 Logic-Gate Modeling	509	(3)
11.9.1 Built-in Logic Models	509	(1)
11.9.2 User-Defined Primitives	510	(2)
11.10 Modeling Delay	512	(3)
11.10.1 Net and Gate Delay	512	(1)
11.10.2 Pin-to-Pin Delay	513	(2)
11.11 Altering Parameters	515	(1)
11.12 A Viterbi Decoder	515	(17)
11.12.1 Viterbi Encoder	515	(4)
11.12.2 The Received Signal	519	(2)
11.12.3 Testing the System	521	(2)
11.12.4 Verilog Decoder Model	523	(9)
11.13 Other Verilog Features	532	(9)
11.13.1 Display Tasks	533	(1)
11.13.2 File I/O Tasks	533	(1)
11.13.3 Timescale, Simulation, and Timing-Check Tasks	534	(3)
11.13.4 PLA Tasks	537	(1)
11.13.5 Stochastic Analysis Tasks	538	(1)
11.13.6 Simulation Time Functions	539	(1)
11.13.7 Conversion Functions	539	(1)
11.13.8 Probability Distributions Functions	540	(1)
11.13.9 Programming Language Interface	541	(1)
11.14 Summary	541	(2)
11.15 Problems	543	(14)
11.15.1 The Viterbi Decoder	556	(1)
11.16 Bibliography	557	(1)
11.17 References	557	(2)
12 LOGIC SYNTHESIS	559	(82)
12.1 A Logic-Synthesis Example	560	(1)
12.2 A Comparator/MUX	561	(8)
12.2.1 An Actel Version of the Comparator/MUX	567	(2)
12.3 Inside a Logic Synthesizer	569	(3)
12.4 Synthesis of the Viterbi Decoder	572	(8)
12.4.1 ASIC I/O	572	(3)
12.4.2 Flip-Flops	575	(1)
12.4.3 The Top-Level Model	575	(5)
12.5 Verilog and Logic Synthesis	580	(13)
12.5.1 Verilog Modeling	580	(1)
12.5.2 Delays in Verilog	581	(1)
12.5.3 Blocking and Nonblocking Assignments	582	(1)
12.5.4 Combinational Logic in Verilog	582	(2)
12.5.5 Multiplexers In Verilog	584	(1)
12.5.6 The Verilog Case Statement	585	(1)
12.5.7 Decoders In Verilog	586	(1)
12.5.8 Priority Encoder in Verilog	587	(1)
12.5.9 Arithmetic in Verilog	587	(2)
12.5.10 Sequential Logic in Verilog	589	(1)
12.5.11 Component Instantiation in Verilog	590	(1)
12.5.12 Datapath Synthesis in Verilog	591	(2)
12.6 VHDL and Logic Synthesis	593	(12)
12.6.1 Initialization and Reset	593	(1)
12.6.2 Combinational Logic Synthesis in VHDL	594	(1)
12.6.3 Multiplexers in VHDL	594	(1)
12.6.4 Decoders in VHDL	595	(2)
12.6.5 Adders in VHDL	597	(1)
12.6.6 Sequential Logic in VHDL	597	(1)
12.6.7 Instantiation in VHDL	598	(3)
12.6.8 Shift Registers and Clocking in VHDL	601	(2)
12.6.9 Adders and Arithmetic Functions	603	(1)
12.6.10 Adder/Subtracter and Don't Cares	604	(1)
12.7 Finite-State Machine Synthesis	605	(6)
12.7.1 FSM Synthesis in Verilog	607	(1)
12.7.2 FSM Synthesis in VHDL	608	(3)
12.8 Memory Synthesis	611	(3)
12.8.1 Memory Synthesis in Verilog	611	(1)
12.8.2 Memory Synthesis in VHDL	612	(2)
12.9 The Multiplier	614	(5)
12.9.1 Messages During Synthesis	617	(2)
12.10 The Engine Controller	619	(1)
12.11 Performance-Driven Synthesis	620	(5)
12.12 Optimization of the Viterbi Decoder	625	(3)
12.13 Summary	628	(1)
12.14 Problems	629	(9)
12.15 Bibliography	638	(1)
12.16 References	639	(2)
13 SIMULATION	641	(70)
13.1 Types of Simulation	641	(2)
13.2 The Comparator/MUX Example	643	(9)
13.2.1 Structural Simulation	644	(3)
13.2.2 Static Timing Analysis	647	(1)
13.2.3 Gate-Level Simulation	648	(2)
13.2.4 Net Capacitance	650	(2)
13.3 Logic Systems	652	(4)
13.3.1 Signal Resolution	653	(1)
13.3.2 Logic Strength	653	(3)
13.4 How Logic Simulation Works	656	(3)
13.4.1 VHDL Simulation Cycle	658	(1)
13.4.2 Delay	658	(1)
13.5 Cell Models	659	(10)
13.5.1 Primitive Models	659	(1)
13.5.2 Synopsys Models	660	(1)
13.5.3 Verilog Models	661	(2)
13.5.4 VHDL Models	663	(1)
13.5.5 VITAL Models	664	(3)
13.5.6 SDF in Simulation	667	(2)
13.6 Delay Models	669	(6)
13.6.1 Using a Library Data Book	670	(2)
13.6.2 Input-Slope Delay Model	672	(2)
13.6.3 Limitations of Logic Simulation	674	(1)
13.7 Static Timing Analysis	675	(7)
13.7.1 Hold Time	678	(1)
13.7.2 Entry Delay	679	(1)
13.7.3 Exit Delay	680	(1)
13.7.4 External Setup Time	681	(1)
13.8 Formal Verification	682	(6)
13.8.1 An Example	682	(2)
13.8.2 Understanding Formal Verification	684	(1)
13.8.3 Adding an Assertion	685	(2)
13.8.4 Completing a Proof	687	(1)
13.9 Switch-Level Simulation	688	(1)
13.10 Transistor-Level Simulation	689	(7)
13.10.1 A PSpice Example	689	(3)
13.10.2 SPICE Models	692	(4)
13.11 Summary	696	(1)
13.12 Problems	696	(12)
13.13 Bibliography	708	(1)
13.14 References	708	(3)
14 TEST	711	(94)
14.1 The Importance of Test	712	(2)
14.2 Boundary-Scan Test	714	(22)
14.2.1 BST Cells	716	(2)
14.2.2 BST Registers	718	(1)
14.2.3 Instruction Decoder	719	(3)
14.2.4 TAP Controller	722	(2)
14.2.5 Boundary-Scan Controller	724	(3)
14.2.6 A Simple Boundary-Scan Example	727	(5)
14.2.7 BSDL	732	(4)
14.3 Faults	736	(9)
14.3.1 Reliability	736	(1)
14.3.2 Fault Models	737	(1)
14.3.3 Physical Faults	738	(2)
14.3.4 Stuck-at Fault Model	740	(1)
14.3.5 Logical Faults	741	(1)
14.3.6 IDDQ Test	742	(1)
14.3.7 Fault Collapsing	743	(1)
14.3.8 Fault-Collapsing Example	743	(2)
14.4 Fault Simulation	745	(10)
14.4.1 Serial Fault Simulation	747	(1)
14.4.2 Parallel Fault Simulation	747	(1)
14.4.3 Concurrent Fault Simulation	747	(1)
14.4.4 Nondeterministic Fault Simulation	748	(1)
14.4.5 Fault-Simulation Results	748	(1)
14.4.6 Fault-Simulator Logic Systems	749	(2)
14.4.7 Hardware Acceleration	751	(1)
14.4.8 A Fault-Simulation Example	752	(2)
14.4.9 Fault Simulation in an ASIC Design Flow	754	(1)
14.5 Automatic Test-Pattern Generation	755	(9)
14.5.1 The D-Calculus	755	(2)
14.5.2 A Basic ATPG Algorithm	757	(2)
14.5.3 The PODEM Algorithm	759	(2)
14.5.4 Controllability and Observability	761	(3)
14.6 Scan Test	764	(2)
14.7 Built-in Self-test	766	(12)
14.7.1 LFSR	766	(1)
14.7.2 Signature Analysis	766	(1)
14.7.3 A Simple BIST Example	767	(1)
14.7.4 Aliasing	768	(3)
14.7.5 LFSR Theory	771	(2)
14.7.6 LFSR Example	773	(2)
14.7.7 MISR	775	(3)
14.8 A Simple Test Example	778	(13)
14.8.1 Test-Logic Insertion	778	(2)
14.8.2 How the Test Software Works	780	(7)
14.8.3 ATVG and Fault Simulation	787	(1)
14.8.4 Test Vectors	787	(2)
14.8.5 Production Tester Vector Formats	789	(2)
14.8.6 Test Flow	791	(1)
14.9 The Viterbi Decoder Example	791	(3)
14.10 Summary	794	(1)
14.11 Problems	794	(6)
14.12 Bibliography	800	(1)
14.13 References	801	(4)
15 ASIC CONSTRUCTION	805	(48)
15.1 Physical Design	805	(2)
15.2 CAD Tools	807	(2)
15.2.1 Methods and Algorithms	808	(2)
15.3 System Partitioning	809	(2)
15.4 Estimating ASIC Size	811	(5)
15.5 Power Dissipation	816	(4)
15.5.1 Switching Current	816	(1)
15.5.2 Short-Circuit Current	817	(1)
15.5.3 Subthreshold and Leakage Current	818	(2)
15.6 FPGA Partitioning	820	(4)
15.6.1 ATM Simulator	820	(3)
15.6.2 Automatic Partitioning with FP-GAs	823	(1)
15.7 Partitioning Methods	824	(14)
15.7.1 Measuring Connectivity	824	(2)
15.7.2 A Simple Partitioning Example	826	(1)
15.7.3 Constructive Partitioning	827	(1)
15.7.4 Iterative Partitioning Improvement	828	(1)
15.7.5 The Kernighan--Lin Algorithm	829	(5)
15.7.6 The Ratio-Cut Algorithm	834	(1)
15.7.7 The Look-ahead Algorithm	835	(1)
15.7.8 Simulated Annealing	836	(1)
15.7.9 Other Partitioning Objectives	837	(1)
15.8 Summary	838	(1)
15.9 Problems	838	(12)
15.10 Bibliography	850	(1)
15.11 References	851	(2)
16 FLOORPLANNING AND PLACEMENT	853	(56)
16.1 Floorplanning	853	(20)
16.1.1 Floorplanning Goals and Objectives	854	(2)
16.1.2 Measurement of Delay in Floorplanning	856	(3)
16.1.3 Floorplanning Tools	859	(2)
16.1.4 Channel Definition	861	(3)
16.1.5 I/O and Power Planning	864	(5)
16.1.6 Clock Planning	869	(4)
16.2 Placement	873	(21)
16.2.1 Placement Terms and Definitions	873	(3)
16.2.2 Placement Goals and Objectives	876	(1)
16.2.3 Measurement of Placement Goals and Objectives	877	(5)
16.2.4 Placement Algorithms	882	(3)
16.2.5 Eigenvalue Placement Example	885	(2)
16.2.6 Iterative Placement Improvement	887	(3)
16.2.7 Placement Using Simulated Annealing	890	(1)
16.2.8 Timing-Driven Placement Methods	891	(2)
16.2.9 A Simple Placement Example	893	(1)
16.3 Physical Design Flow	894	(1)
16.4 Information Formats	895	(3)
16.4.1 SDF for Floorplanning and Placement	895	(1)
16.4.2 PDEF	896	(1)
16.4.3 LEF and DEF	897	(1)
16.5 Summary	898	(1)
16.6 Problems	898	(8)
16.7 Bibliography	906	(1)
16.8 References	906	(3)
17 ROUTING	909	(52)
17.1 Global Routing	910	(12)
17.1.1 Goals and Objectives	911	(1)
17.1.2 Measurement of Interconnect Delay	912	(3)
17.1.3 Global Routing Methods	915	(1)
17.1.4 Global Routing Between Blocks	916	(2)
17.1.5 Global Routing Inside Flexible Blocks	918	(2)
17.1.6 Timing-Driven Methods	920	(1)
17.1.7 Back-annotation	921	(1)
17.2 Detailed Routing	922	(13)
17.2.1 Goals and Objectives	926	(1)
17.2.2 Measurement of Channel Density	927	(1)
17.2.3 Algorithms	928	(1)
17.2.4 Left-Edge Algorithm	928	(1)
17.2.5 Constraints and Routing Graphs	928	(3)
17.2.6 Area-Routing Algorithms	931	(2)
17.2.7 Multilevel Routing	933	(1)
17.2.8 Timing-Driven Detailed Routing	933	(1)
17.2.9 Final Routing Steps	934	(1)
17.3 Special Routing	935	(4)
17.3.1 Clock Routing	935	(1)
17.3.2 Power Routing	936	(3)
17.4 Circuit Extraction and DRC	939	(7)
17.4.1 SPF, RSPF, and DSPF	939	(5)
17.4.2 Design Checks	944	(1)
17.4.3 Mask Preparation	945	(1)
17.5 Summary	946	(1)
17.6 Problems	947	(9)
17.7 Bibliography	956	(1)
17.8 References	957	(4)
A VHDL RESOURCES	961	(18)
1.1 BNF	961	(2)
1.2 VHDL Syntax	963	(10)
1.3 BNF Index	973	(1)
1.4 Bibliography	973	(3)
1.5 References	976	(3)
B VERILOG HDL RESOURCES	979	(21)
2.1 Explanation of the Verilog HDL BNF	979	(1)
2.2 Verilog HDL Syntax	980	(14)
2.3 BNF Index	994	(1)
2.4 Verilog HDL LRM	994	(3)
2.5 Bibliography	997	(2)
2.6 References	999	(1)
GLOSSARY	1000	(6)
INDEX	1006

Excerpts

In 1988 I began to teach full-custom VLSI design. In 1990 I started teaching ASIC design instead, because my students found it easier to get jobs in this field. I wrote a proposal to The National Science Foundation (NSF) to use electronic distribution of teaching material. Dick Lyon helped me with preparing the first few CD-ROMs at Apple, but Chuck Seitz, Lynn Conway, and others explained to me that I was facing a problem that Carver Mead and Lynn had experienced in trying to get the concept of multichip wafers adopted. It was not until the publication of the Mead-Conway text that people accepted this new idea. It was suggested that I must generate interest using a conventional format before people would use my material in a new one (CD-ROM or the Internet). In 1992 I stopped writing papers and began writing this book-a result of my experiments in computer-based education. I have nearly finished this book twice. The first time was a copy of my notes. The second time was just before the second edition of Weste and Eshragian was published-a hard act to follow. In order to finish in 1997 I had to stop updating and including new ideas and material and now this book consists of three parts: Chapters 1-8 are an introduction to ASICs, 9-14 cover ASIC logical design, and 15-17 cover the physical design of ASICs. The book is intended for a wide audience. It may be used in an undergraduate or graduate course. It is also intended for those in industry who are involved with ASICs. Another function of this book is an "ASIC Encyclopedia," and therefore I have kept the background material needed to a minimum. The book makes extensive use of industrial tools and examples. The examples in Chapters 2 and 3 use tools and libraries from MicroSim (PSpice), Meta Software (HSPICE), Compass Design Automation (standard-cell and gate-array libraries), and Tanner Research (L-Edit). The programmable ASIC design examples in Chapter 4-8 use tools from Compass, Synopsys, Actel, Altera, and Xilinx. The examples in Chapter 9 (covering low-level design entry) used tools from Exemplar, MINC, AMD, UC Berkeley, Compass, Capilano, Mentor Graphics Corporation, and Cadence Design Automation. The VHDL examples in Chapter 10 were checked using QuickVHDL from Mentor, V-System Plus from Model Technology, and Scout from Compass. The Verilog examples in Chapter 11 were checked using Verilog-XL from Cadence, V-System Plus, and VeriWell from Wellspring Solutions. The logic synthesis examples in Chapter 12 were checked with the ASIC Synthesizer product family from Compass and tools from Mentor, Synopsys, and UC Berkeley. The simulation examples in Chapter 13 were checked with QuickVHDL, V-System/Plus, PSpice, Verilog-XL, DesignWorks from Capilano Computing, CompassSim, QSim, MixSim, and HSPICE. The test examples in Chapter 14 were checked using test software from Compass, Cadence, Mentor, Synopsys and Capilano''s DesignWorks. The physical design examples in Chapters 15-17 were generated and tested using Preview, Gate Ensemble, and Cell Ensemble (Cadence) as well as ChipPlanner, ChipCompiler, and PathFinder (Compass). All these tools are installed at the University of Hawaii. I wrote the text using FrameMaker. This allows me to project the text and figures using an LCD screen and an overhead projector. I used a succession of Apple Macintosh computers: a PowerBook 145, a 520, and lastly a 3400 with 144 MB of RAM, which made it possible for me to create updates to the index in just under one minute. Equations are "live" in FrameMaker. Thus, can be updated in a lecture and the new result displayed. The circuit layouts are color EPS files with enhanced B&W PICT previews created using L-Edit from Tanner Research. All of the Verilog and VHDL code examples, compiler and simulation input/output, and the layout CIF that were used in the final version are included as conditional (hidden) text in the FrameMaker document, which is approximately 200 MB and just over 6,000 pages (my original source material spans fourteen 560 MB optical disks). Software can operate on the hidden text, allowing, for example, a choice of simulators to run the HDL code live in class. I converted draft versions of the VHDL and Verilog LRMs and related standards to FrameMaker and built hypertext links to my text, but copyright problems will have to be solved before this type of material may be published. I drew all the figures using FreeHand. They are "layered" allowing complex drawings to be built-up slowly or animated by turning layers on or off. This is difficult to utilize in book form, but can be done live in the classroom. A course based on FPGAs can use Chapter 1 and Chapters 4-8. A course using commercial semicustom ASIC design tools may use Chapters 1-2 or Chapters 1-3 and then skip to Chapter 9 if you use schematic entry, Chapter 10 (if you use VHDL), or Chapter 11 (if you use Verilog) together with Chapter 12. All classes can use Chapters 13 and 14. FPGA-based classes may skim Chapters 15-17, but classes in semicustom design should cover these chapters. The chapter dependencies-Y (X) means Chapter Y depends on X-are approximately: 1, 2(1), 3(2), 4(2), 5(4), 6(5), 7(6), 8(7), 9(2), 10(2), 11(2), 12(10 or 11), 13(2), 14(13), 15(2), 16(15), 17(16). I used the following references to help me with the orthography of complex terms, style, and punctuation while writing: Merriam-Webster''s Collegiate Dictionary, 10th edition, 1996, Springfield, MA: Merriam-Webster, ISBN 0-87779-709-9, PE1628.M36; The Chicago Manual of Style, 14th edition, Chicago: University of Chicago Press, 1993, ISBN 0-226-10389-7, Z253.U69; and Merriam-Webster''s Standard American Style Manual, 1985, Springfield, MA: Merriam-Webster, ISBN 0-87779-133-3, PN147.W36. A particularly helpful book on technical writing is BUGS in Writing by Lyn DuprE, 1995, Reading, MA: Addison-Wesley, ISBN 0-201-60019-6, PE1408.D85 (this book grew from Lyn DuprE''s unpublished work, Style SomeX, which I used). The bibliography at the end of each chapter provides alternative sources if you cannot find what you are looking for. I have included the International Standard Book Number (ISBN) and Library of Congress (LOC) Call Number for books, and the International Standard Serial Number (ISSN) for journals (see the LOC information system, LOCIS, at http://www.loc.gov). I did not include references to material that I could not find myself (except where I have noted in the case of new or as yet unpublished books). The electronic references given in this text have (a last) access date of 4/19/97 and omit enclosing<>if the reference does not include spaces. I receive a tremendous level of support and cooperation from industry in my work. I thank the following for help with this project: Cynthia Benn and Lyn DuprE for editing; Helen Goldstein, Peter Gordon, Susan London-Payne, Tracy Russ, and Juliet Silveri, all at Addison-Wesley; Matt Bowditch and Kim Arney at Argosy; Richard Lyon, Don North, William Rivard, Glen Stone, the managers of the Newton group, and many others at Apple Computer who provided financial support; Apple for providing support in the form of software and computers; Bill Becker, Fern Forcier, Donna Isidro, Mike Kliment, Paul McLellan, Tom Schaefer, Al Stein, Rich Talburt, Bill Walker, and others at Compass Design Automation and VLSI Technology for providing the opportunity for me to work on this book over many years and allowing me to test material inside these companies and on lecture tours they sponsored; Chuck Seitz at Caltech; Joseph Cavallaro, Bernie Chern, Jerry Dillion, Mike Foster, and Paul Hulina at the NSF; the NSF for financial support with a Presidential Young Investigator Award; Jim Rowson and Doug Fairbairn; Constantine Anagnostopolous, Pin Tschang and members of the ASIC design groups at Kodak for financial support; the disk-drive design group at Digital Equipment Corp. (Massachusetts), Hewlett-Packard, and Sun M