Architecture of Computing Systems - ARCS 2010 : 23rd International Conference, Hannover, Germany, February 22-25, 2010, Proceedings

by Muller-schloer, Christian; Karl, Wolfgang; Yehia, Sami

• ISBN13: 9783642119491
• ISBN10: 3642119492
• Format: Paperback
• Copyright: 2010-02-27
• Publisher: Springer-Verlag New York Inc

Summary

This book constitutes the refereed proceedings of the 23rd InternationalConference on Architecture of Computing Systems, ARCS 2010, held inHannover, Germany, in February 2010.The 20 revised full papers presented together with 1 keynote lecture werecarefully reviewed and selected from 55 submissions. This year's specialfocus is set on heterogeneous systems. The papers are organized in topicalsections on processor design, embedded systems, organic computing andself-organization, processor design and transactional memory, energymanagement in distributed environments and ad-hoc grids, performancemodeling and benchmarking, as well as accelerators and GPUs.

Table of Contents

Keynote
HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors	p. 1
Processor Design
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT	p. 2
Complexity-Effective Rename Table Design for Rapid Speculation Recovery	p. 15
An Embedded GC Module with Support for Multiple Mutators and Weak References	p. 25
Embedded Systems
A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems	p. 37
Autonomic Workload Management for Multi-core Processor Systems	p. 49
Firefly Flashing Synchronization as Inspiration for Self-synchronization of Walking Robot Gait Patterns Using a Decentralized Robot Control Architecture	p. 61
Organic Computing and Self-organization
The JoSchKa System: Organic Job Distribution in Heterogeneous and Unreliable Environments	p. 73
On Deadlocks and Fairness in Self-organizing Resource-Flow Systems	p. 87
Ad-Hoc Information Spread between Mobile Devices: A Case Study in Analytical Modeling of Controlled Self-organization in IT Systems	p. 101
Processor Design and Transactional Memory
MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance	p. 113
Exploiting Inactive Rename Slots for Detecting Soft Errors	p. 126
Efficient Transaction Nesting in Hardware Transactional Memory	p. 138
Energy Management in Distributed Environments and Ad-Hoc Grids
Decentralized Energy-Management to Control Smart-Home Architectures	p. 150
EnergySaving Cluster Roll: Power Saving System for Clusters	p. 162
Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids	p. 174
Performance Modelling and Benchmarking
Compiler-Directed Performance Model Construction for Parallel Programs	p. 187
A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces	p. 199
JetBench: An Open Source Real-Time Multiprocessor Benchmark	p. 211
Accelerators and GPUs
A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics	p. 222
Optimizing Stencil Application on Multi-thread GPU Architecture Using Stream Programming Model	p. 234
Author Index	p. 247
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